Instrumented Multi-Stage Word-Length Optimization

Osborne, W.; Coutinho, J.G.F.; Cheung, Ray C. C.; Luk, Wayne; Mencer, Oskar

doi:10.1109/fpt.2007.4439236

Cited by 16 publications

(20 citation statements)

References 11 publications

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“…It can be used to reduce dynamic power consumption to prevent signal transitions by disabling the clock for the inactive regions. The circuitry in an operator is gated when not in use if it can be combined with word-length optimization [62] . -It is found that, at a given clock speed, pipelining which is a simple and effective way of reducing glitching can reduce the amount of energy per operation by between 40% and 90% for applications such as integer multiplication, CORDIC, triple DES, and FIR filters [63] .…”

Section: Power Reduction At System Level Designmentioning

confidence: 99%

“… Techniques with run-time reconfigurability -Runtime reconfiguration with word-length optimization can be combined to adopt the smallest design at a given time, as long as the energy reduction in execution is greater than the energy overhead for reconfiguration [62] . -In order to adapt to run-time conditions, runtime reconfiguration can be applied to change a design.…”

Section: Power Reduction At System Level Designmentioning

confidence: 99%

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Reduction of Power Consumption in FPGAs - An Overview

Grover¹,

Soni²

2012

IJIEEB

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-Field Programmable Gate Arrays FPGAs are highly desirable for implementation of digital systems due to their flexibility, programmability and low end product life cycle. In more than 20 years since the introduction of FPGA, research and development has produced dramatic improvements in FPGA speed and area efficiency, narrowing the gap between FPGAs and ASICs and making FPGAs the platform of choice for implementing digital circuits. FPGAs hold significant promise as a fast to market replacement. Unfortunately, the advantages of FPGAs are offset in many cases by their high power consumption and area. The goal is to reduce the power consumption without sacrificing much performance or incurring a large chip area so that the territories of FPGAs applications can expand more effectively. Reducing the power of FPGAs is the key to lowering packaging and cooling costs, improving device reliability, and opening the door to new markets such as mobile electronics. This paper presents the tips to lower down the static and dynamic power dissipation in FPGAs. It gives an overview of various techniques at system, device, and circuit and architecture level used for reduction of power consumption of FPGAs and their outcomes.

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Section: Power Reduction At System Level Designmentioning

confidence: 99%

Section: Power Reduction At System Level Designmentioning

confidence: 99%

Reduction of Power Consumption in FPGAs - An Overview

Grover¹,

Soni²

2012

IJIEEB

View full text Add to dashboard Cite

show abstract

“…Similarly, Lee et al [11] develop an automatic optimization approach, which is called MiniBit, to produce accuracy-guaranteed solutions, and area is minimized while meeting an error constraint. Osborne [12] uses both IA and AA for range analysis for different situations. Computation using either of the two methods in the design is time-consuming.…”

Section: Related Workmentioning

confidence: 99%

“…It can be usually classified into dynamic analysis [2][3][4][5][6][7] and static analysis [8][9][10][11][12][13][14][15][16][17][18][19][20]. By analyzing a large set of stimuli signals, dynamic analysis is applicable to all types of systems.…”

mentioning

confidence: 99%

“…Comparatively, the static analysis is an automated and efficient word-length optimization method and more applicable to large designs when compared to dynamic analysis. The static analysis mainly uses the characteristics of the input signals to estimate the word length conservatively, which can result in overestimation [12] to some extent. As a part of word-length optimization, the range analysis can also been classified in the same way.…”

mentioning

confidence: 99%

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A refined affine approximation method of multiplication for range analysis in word-length optimization

Sun

Zhang

Cui

2014

EURASIP J. Adv. Signal Process.

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Affine arithmetic (AA) is widely used in range analysis in word-length optimization of hardware designs. To reduce the uncertainty in the AA and achieve efficient and accurate range analysis of multiplication, this paper presents a novel refined affine approximation method, Approximation Affine based on Space Extreme Estimation (AASEE). The affine form of multiplication is divided into two parts. The first part is the approximate affine form of the operation. In the second part, the equivalent affine form of the estimated range of the difference, which is introduced by the approximation, is represented by an extra noise symbol. In AASEE, it is proven that the proposed approximate affine form is the closest to the result of multiplication based on linear geometry. The proposed equivalent affine form of AASEE is more accurate since the extreme value theory of multivariable functions is used to minimize the difference between the result of multiplication and the approximate affine form. The computational complexity of AASEE is the same as that of trivial range estimation (AATRE) and lower than that of Chebyshev approximation (AACHA). The proposed affine form of multiplication is demonstrated with polynomial approximation, B-splines, and multivariate polynomial functions. In experiments, the average of the ranges derived by AASEE is 59% and 89% of that by AATRE and AACHA, respectively. The integer bits derived by AASEE are 2 and 1 b less than that by AATRE and AACHA at most, respectively.

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Resource optimization for emulation of behavioral models of mixed signal circuits on FPGA: a case study of DC–DC buck converter

Bhattacharya

Kumar

Biswas

2017

Circuit Theory & Apps

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Summary This paper presents a semi‐automated word‐length optimization framework to reduce field‐programmable gate array (FPGA) resource utilization for FPGA‐based pre‐silicon test emulation of analog and mixed signal circuits while achieving the desired accuracy and overcoming long optimization time. Although high‐level behavioral models exist for modeling analog and mixed signal circuits, these comprise many complex differential equations which cannot be realized implicitly using Boolean logic (which is the basic functional block of an FPGA) on an FPGA. So, a more convenient way is explored to map analog circuits into digital domain by converting them into fixed‐point architectures because of its advantage of manipulating data with lower word‐length. To address the loss of accuracy due to finite word‐length effects and limited reconfigurable resources, word‐lengths are optimized under the constraint of given performance metrics. The proposed technique built in MATLAB/Simulink environment with Xilinx System Generator support is illustrated with the help of a case study of a peak‐current‐mode‐controlled buck‐type switching converter implemented on Xilinx Virtex™‐5 FPGA. To illustrate the applicability of this environment for pre‐silicon test development, well‐accepted fault models are emulated with the help of non‐ideal model of a buck converter. The emulation results are seen to be close to that of a post‐fabricated power converter in the presence of faults. Experimental results show that FPGA resource utilization can be reduced significantly while achieving the desired performance accuracy under the constraint of multiple error metrics. Copyright © 2017 John Wiley & Sons, Ltd.

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Instrumented Multi-Stage Word-Length Optimization

Cited by 16 publications

References 11 publications

Reduction of Power Consumption in FPGAs - An Overview

Reduction of Power Consumption in FPGAs - An Overview

A refined affine approximation method of multiplication for range analysis in word-length optimization

Resource optimization for emulation of behavioral models of mixed signal circuits on FPGA: a case study of DC–DC buck converter

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