Integer‐ N charge pump phase locked loop for 2.4 GHz application with a novel design of phase frequency detector

Abstract

In this article, a novel design is presented, for an Integer-N charge pump phase locked loop (PLL). The design is with a resetless phase frequency detector, and with the differential design of charge pump. The voltage-controlled oscillator is of current starved type. The proposed PLL is not having any blind zone and is having near-zero dead zone. When compared to the conventional design, the current mismatch in the charge pump is reduced by 3.21%, and the lock time of the PLL is reduced by 79%. The PLL is intended for 2.4 GHz application, and the obtained lock time is 1.7 μs. The implementation is done with the three-stage ring oscillator, with divider of modulus as 24, in 180 nm TSMC technology. At 1.8 V supply voltage, the circuit consumes 9.72 mW of power.

A high swing charge pump with current mismatch reduction for PLL applications

“…However, the value of these resistors is easily affected by multiple factors. In addition, a common-mode feedback scheme [4], an active feedback circuit [26,27,28] and a gate bias technique [29] compensate the current mismatch based on the operational amplifier or the bulk driven cascode current mirror, but the reduction of the output dynamic voltage range is still inevitable in these methods.…”