Integer-pixel motion estimation H.264/AVC accelerator architecture with optimal memory management

Campos, Armando Mora; Ballester-Merelo, Francisco José; Peiró, Marcos A. Martínez; Esteve, Jose Antonio Canals

doi:10.1016/j.micpro.2007.06.002

Cited by 11 publications

(6 citation statements)

References 8 publications

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“…It can process 1080HD video streams at that clock frequency. [21] When compared to the architecture in [7], the proposed work considerably decreases the latency by fifth from 4096, the use of three parallel processor modules in our approach requires more resources such as LUTs compared to [7], the maximum operating frequency is slightly increased and the search range has risen from 16 × 16 to 48 × 48. Table 3 shows the comparison between our proposed architecture of IME based on Virtex 7 FPGA, and previously published ME architectures based on ASIC and FPGA platforms.…”

Section: Implementation Resultsmentioning

confidence: 98%

“…It utilizes 27,608 LUTs, 20,233 register bits, 5 blocks SRAMs are used to store the SW and the 16 × 16 current block. [7,17,21] The first selected architecture Table 1. It can process 1080HD video streams at that clock frequency.…”

Section: Implementation Resultsmentioning

confidence: 99%

“…Maximum clock frequency of the proposed architecture is 473 MHz. designs in [17,21], the number of clock cycles is reduced to half reaching 784 cycles for processing one MB; but the required resources are increased due to the use of three processor modules instead of one in comparative architecture. Table 2 compares between the proposed architecture and the three most interesting ME architectures previously published.…”

Section: Implementation Resultsmentioning

confidence: 99%

See 2 more Smart Citations

Real-time hardware implementation of a speed FSBMA used in H.264/AVC

Yahi

Messaoudi

Toumi

et al. 2015

International Journal of Computers and Applications

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a lerICa laboratory, Badji mokhtar university, annaba, algeria; b le2I laboratory, Burgundy university, dijon, france ABSTRACT Nowadays, H.264/AVC reaches very high resolutions, flexible depending on the application, which particularly leads to a very large amount of data compression. The motion estimation defines the most-complex process and the most interesting at the same time; its complexity appears with a consumption of more than 60% of total encoding time which make it difficult to achieve real-time encoding required in many video applications, but the interesting part is the flexibility to make its implementation variant according to the application. For this purpose, the following paper presents a speed real-time hardware implementation of integer motion estimation used in H.264/AVC, the method is based on the full-search block-matching algorithm. The proposed architecture calculates best motion vector using a parallel process. It is composed of three processor modules and a comparator three values. Implementation results based on Field Programmable Gate Array devices uses Xilinx Virtex7 XC7VX550T show performance characteristics like low latency, high processing speed reaching 473 MHz of frequency. The processing capacity is up to 1080HD video streams with a search range of 48 × 48.

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Section: Implementation Resultsmentioning

confidence: 98%

Section: Implementation Resultsmentioning

confidence: 99%

Section: Implementation Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Real-time hardware implementation of a speed FSBMA used in H.264/AVC

Yahi

Messaoudi

Toumi

et al. 2015

International Journal of Computers and Applications

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show abstract

“…But its resource cost is up to 330K. In the paper of Campos et al [9], the utilization of PE array reaches almost 100%. And they also gave the memory structure and management, but it also cost much logic resource.…”

Section: Full Search Schemementioning

confidence: 99%

A low cost hardware oriented motion estimation algorithm for HDTV

Teng

Zhang

et al. 2009

Proceedings of the First ACM/SIGEVO Summit on Genetic and Evolutionary Computation

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A hardware oriented Motion Estimation (ME) algorithm which can be combined into FPGA based SDTV or HDTV encoder is proposed. The present Full Search (FS) algorithm cost too much logic resource, thus it limits the application of real time video encoder. And all of the fast algorithms are difficult to reuse data between candidates, thus they are not suitable for ASIC or FPGA implementation. After reviewing the previous ME algorithms and researching the distribution of Motion Vector (MV), we optimize the hardware ME by selecting block-matching candidates in the Search Window (SW). Then a novel Big-Hexagon-Like searching route is proposed. And the number of PE arrays is decreased from 8 to 2. Therefore, the high logic resource cost of ME is alleviated notably. And the method of data reusing is also proposed. Then a hardware architecture is proposed. We have tested the proposal with High definition, CIF and QCIF video sequences. Comparing the test result with F017 and Diamond algorithms, the proposal has a comparative RDO (Rate-Distortion Optimization) performance to F017 and is better than Diamond which is adopted by T264. An FPGA implementation of the proposed algorithm is realized, the result of implementation shows that the equivalent gates count is reduced to 121K.

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“…Fast ME algorithms [1], [2], reduce the complexity and keep the resulting QoS close to that of the Full Search algorithm. Designers of ME architectures concentrate on solving the problem of real-time performance and also on optimizing the hardware resources of Full Search architectures [3], [4], [5], specific fast ME implementations [6], [7], or programmable organizations [8], [9], [10] allowing the choice of the most suitable ME algorithm to each application.…”

Section: Introductionmentioning

confidence: 99%

Programmable Motion Estimation architecture

Drolapas

Lentaris

Reisis

2009

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)

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This paper presents a real-time Motion Estimation architecture with improved hardware cost. The design bases on a parallel memory organization minimizing the resources required to support integer and sub-pixel modes of search, while it sustains the required throughput of pixels to the SAD calculator. A speculative execution technique improves the number of cycles required by the search process. The architecture is programmable including an instruction set for actions common to all the block-matching techniques, while circuits introduced at compile time accommodate individual actions of the most demanding algorithms such as MVFAST and PMVFAST. A FPGA implementation validates HDTV video performance.

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Integer-pixel motion estimation H.264/AVC accelerator architecture with optimal memory management

Cited by 11 publications

References 8 publications

Real-time hardware implementation of a speed FSBMA used in H.264/AVC

Real-time hardware implementation of a speed FSBMA used in H.264/AVC

A low cost hardware oriented motion estimation algorithm for HDTV

Programmable Motion Estimation architecture

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