Integer vs. Floating-Point Processing on Modern FPGA Technology

Hettiarachchi, Don Lahiru Nirmal; Davuluru, Venkata Salini Priyamvada; Balster, Eric J.

doi:10.1109/ccwc47524.2020.9031118

Cited by 12 publications

(6 citation statements)

References 13 publications

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“…FPGA resource utilization report shows the usage statistics of Adaptive Look-Up Tables (ALUTs), registers, logic utilization, DSP Blocks, and RAM Blocks for kernel design. However, the implemented FPGA Performance Metric (FPM) only uses logic utilization and kernel F M AX [42]. Generally, FPGA devices consist of thousands of Logic Array Blocks (LABs) that are connected to interconnects.…”

Section: A Fpga Performance Metricmentioning

confidence: 99%

“…In [42], it is shown that even with hardened FPUs, floatingpoint designs that are converted to fixed-point designs use fewer logic resources compared to the floating-point designs. The method is tested with a series of basic arithmetic operations for both floating-point and fixed-point based designs.…”

Section: Yegulalp Et Al Introduces a Fast Back Projection (Fbp)mentioning

confidence: 99%

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Fixed-Point Processing of the SAR Back-Projection Algorithm on FPGA

Hettiarachchi¹,

Balster²

2021

IEEE J. Sel. Top. Appl. Earth Observations Remote Sensing

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Time-domain back projection (BP) is a widely known method used in Synthetic Aperture Radar (SAR) image formation. Despite its advantages over other image formation algorithms, the BP method is hindered due to its computational complexity and its requirement of higher number of operations and processing power. Recently, Field Programmable Gate Array (FPGA) devices have been used for BP acceleration mainly due to their parallel processing capabilities, reconfigurability, scalability, and low power requirement. This paper presents a new Fixed-point based BP (FxBP) design for FPGA devices and a Floating-point based BP (FlBP) design to compare performance. Both designs are developed with N-Dimensional Range (NDR) structure and Single Work Item (SWI) structure using OpenCL. The FPGA performance is evaluated using a FPGA performance metric (FPM). It is shown that FxBP-NDR and FxBP-SWI designs generate high quality back projected images compared to FlBP designs, while saving 16.87% and 42.54% on logic resources and gaining 17.90% and 91.62% on FPGA performance in NDR and SWI, respectively. Obtained results clearly indicate that FPGA devices perform significantly better with FxBP designs compared to FlBP designs, even with hardened FPUs.

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Section: A Fpga Performance Metricmentioning

confidence: 99%

Section: Yegulalp Et Al Introduces a Fast Back Projection (Fbp)mentioning

confidence: 99%

Fixed-Point Processing of the SAR Back-Projection Algorithm on FPGA

Hettiarachchi¹,

Balster²

2021

IEEE J. Sel. Top. Appl. Earth Observations Remote Sensing

Self Cite

View full text Add to dashboard Cite

show abstract

“…FPGA resource utilization report shows the usage statistics of Adaptive Look-Up Tables (ALUTs), registers, logic utilization, DSP Blocks, and RAM Blocks for kernel design. However, the implemented FPGA Performance Metric (FPM) only uses logic utilization and kernel F M AX [38]. Generally, FPGA devices consist of thousands of Logic Array Blocks (LABs) that are connected to interconnects.…”

Section: A Fpga Performance Metricmentioning

confidence: 99%

“…In [38], it is shown that even with hardened FPUs, floatingpoint designs that are converted to fixed-point designs use fewer logic resources compared to the floating-point designs. The method is tested with a series of basic arithmetic operations for both floating-point and fixed-point based designs.…”

Section: Introductionmentioning

confidence: 99%

Fixed Point Processing of the SAR Back Projection Algorithm on FPGA

Hettiarachchi¹,

Balster²

2021

Preprint

Self Cite

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Time-domain back projection (BP) is a widely known method used in Synthetic Aperture Radar (SAR) image formation. Despite its advantages over other image formation algorithms, the BP method is hindered due to its computational complexity and its requirement of higher number of operations and processing power. Recently, Field Programmable Gate Array (FPGA) devices have been used for BP acceleration mainly due to their parallel processing capabilities, reconfigurability, scalability, and low power requirement. This paper presents a new Fixed-point based BP (FxBP) design for FPGA devices and a Floating-point based BP (FlBP) design to compare performance. Both designs are developed with N-Dimensional Range (NDR) structure and Single Work Item (SWI) structure using OpenCL. The FPGA performance is evaluated using a FPGA performance metric (FPM). It is shown that FxBP-NDR and FxBP-SWI designs generate high quality back projected images compared to FlBP designs, while saving 16.87 % and 42.54 % on logic resources and gaining 17.90 % and 91.62 % on FPGA performance in NDR and SWI, respectively. Obtained results clearly indicate that FPGA devices perform significantly better with FxBP designs compared to FlBP designs, even with hardened FPUs.

show abstract

“…As FPGAs continued to grow in size they started to incorporate more and more custom resources such as DSP blocks, BRAMs, and full adders inside the CLBs. These custom resources, often called "hardened" resources, are not programmable devices as they are designed specifically to perform a task [120][121][122]. In addition, FPGA vendors typically provide Intellectual Property (IP) Cores, reusable components that intelligently use the capabilities of the FPGA's Architecture to accomplish specific tasks.…”

Section: Fpga Architecturementioning

confidence: 99%

High-Resolution Otdr With Embedded Precise Fault Analysis

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Integer vs. Floating-Point Processing on Modern FPGA Technology

Cited by 12 publications

References 13 publications

Fixed-Point Processing of the SAR Back-Projection Algorithm on FPGA

Fixed-Point Processing of the SAR Back-Projection Algorithm on FPGA

Fixed Point Processing of the SAR Back Projection Algorithm on FPGA

High-Resolution Otdr With Embedded Precise Fault Analysis

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