Integrated production overlay field-by-field control for leading edge technology nodes

Abstract

As photolithography will continue with 193nm immersion multiple patterning technologies for the leading edge HVM process node, the production overlay requirement for critical layers in logic devices has almost reached the scanner hardware performance limit. To meet the extreme overlay requirements in HVM production environment, this study investigates a new integrated overlay control concept for leading edge technology nodes that combines the run-to-run (R2R) linear or high order control loop, the periodic field-by-field or correction per exposure (CPE) wafer process signature control loop, and the scanner baseline control loop into a single integrated overlay control path through the fab host APC system. The goal is to meet the fab requirements for overlay performance, lower the cost of ownership, and provide freedom of control methodology. In this paper, a detailed implementation of this concept will be discussed, along with some preliminary results.

Run time scanner data analysis for HVM lithography process monitoring and stability control

“…Our investigation of grid matching between these two Tool -E to Golden tools also uncovered a mismatch due to a scan direction dependency. Figure 7, shows this scan direction dependency which was determined to be the root cause of the grid mismatch [4].…”

Precipitation Behaviors of Rapid Thermal Annealing Treated Silicon Wafers under Various Thermal Cycles

“…It has been reported that a higher density of smaller size precipitates act as an obstacle for moving dislocations to propagate (6). The ULSI fabs are practicing various misalignment correction schemes to compensate random errors, which most likely include process-induced errors (7)(8). However, slip-induced displacements, due to their inhomogeneous nature, are hardly correctable by compensation.…”