Integrated Sensor Electronic Front-Ends with Self-X Capabilities

Abstract

The ongoing vivid advance in integration technologies is giving leverage both to computing systems as well as to sensors and sensor systems. Both conventional computing systems as well as innovative computing systems, e.g., following bio-inspiration from nervous systems or neural networks, require efficient interfacing to an increasing diversity of sensors under the constraints of metrology. The realization of sufficiently accurate, robust, and flexible analog front-ends (AFE) is decisive for the overall application system and quality and requires substantial design expertise both for cells in System-on-Chip (SoC) or chips in System-in-Package (SiP) realizations. Adding robustness and flexibility to sensory systems, e.g., for Industry 4.0., by self-X or self-* features, e.g., self-monitoring, -trimming, or -healing (AFEX) approaches the capabilities met in living beings and is pursued in our research. This paper summarizes on two chips, denoted as Universal-Sensor-Interface-with-self-X-properties (USIX) based on amplitude representation and reports on recently identified challenges and corresponding advanced solutions, e.g., on circuit assessment as well as observer robustness for classic amplitude-based AFE, and transition activities to spike domain representation spiking-analog-front-ends with self-X properties (SAFEX) based on adaptive spiking electronics as the next evolutionary step in AFE development. Key cells for AFEX and SAFEX have been designed in XFAB xh035 CMOS technology and have been subject to extrinsic optimization and/or adaptation. The submitted chip features 62,921 transistors, a total area of 10.89 mm2 (74% analog, 26% digital), and 66 bytes of the configuration memory. The prepared demonstrator will allow intrinsic optimization and/or adaptation for the developed technology agnostic concepts and chip instances. In future work, confirmed cells will be moved to complete versatile and robust AFEs, which can serve both for conventional as well as innovative computing systems, e.g., spiking neurocomputers, as well as to leading-edge technologies to serve in SOCs.

Low-Cost Indirect Measurements for Power-Efficient In-Field Optimization of Configurable Analog Front-Ends with Self-X Properties: A Hardware Implementation

“…This paper continues our work previously published in [36] after receiving the manufactured chip from the XFAB foundry using the standard CMOS 0.35 µm technology supported by EUROPRACTICE MPW. For the design and verification process, we utilized the Cadence tools, also provided by EUROPRACTICE.…”

On-Chip Adaptive Implementation of Neuromorphic Spiking Sensory Systems with Self-X Capabilities

“…The three core principles of Jeffress's theory are integrated into the SA-SDC through synapse weights, an array of adaptable coincidence detection, and a winner-takes-all (WTA) mechanism with memory [18]. In our chip, we addressed the aforementioned issues by making two contributions to the universal-sensor-interface with self-X properties (USIX), as described in our earlier publication [16]. The multi-project-chip (MPC) USIX is named as such because we integrated the fundamental blocks of contributions based on amplitude-and spike-domain representation with self-X for analog front-ends (AFE).…”

“…The first contribution pertains to reconfigurable hardware, and its outcomes have already been published in [24]. This paper aims to complement the spiking part using the chip and measurement results of the second contribution in section four of the previous paper [16]. Figure 2a displays the chip layout implementation, while Figure 2b shows the specifics of the post-manufacturing chip that incorporates the essential components of the adaptive neuromorphic spiking sensory system, including neurons, synapses, adaptive coincidence detection (ACD), and SA-SRC.…”

“…These properties are inherent in any neural spiking model. We modified the Indiveri neuron model in [16] to fulfill the needs of ACD and enhance power efficiency, area utilization, and processing speed. A schematic of the modified neuron model can be observed in Figure 6.…”

“…The ability to create an accurate, robust, and adaptable design is crucial for the overall application system's success. Consequently, we have integrated the essential blocks of our proposed neuromorphic spiking sensory system that possesses self-X properties and utilizes either spike or time-coded signals in our chip [16]. This system was designed with a technology-agnostic feature that remains resilient even with technology scaling.…”