Integrating NVIDIA Deep Learning Accelerator (NVDLA) with RISC-V SoC on FireSim

Farshchi, Farzad; Huang, Qijing; Yun, Heechul

doi:10.48550/arxiv.1903.06495

Cited by 1 publication

(1 citation statement)

References 9 publications

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“…To avoid overfitting, we include hardware designs from various classes of applications and varying design complexities. We use many hardware designs from open-source projects and open-source collections such as Chipyard [1] and NVDLA [7]. MachSuite [25] also provides opensource implementations of commonly accelerated low-level kernels.…”

Section: Hardware Design Dataset Generationmentioning

confidence: 99%

SNS's not a synthesizer

Kjellqvist

Wills

2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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The number of transistors that can fit on one monolithic chip has reached billions to tens of billions in this decade thanks to Moore's Law. With the advancement of every technology generation, the transistor counts per chip grow at a pace that brings about exponential increase in design time, including the synthesis process used to perform design space explorations. Such a long delay in obtaining synthesis results hinders an efficient chip development process, significantly impacting time-to-market. In addition, these large-scale integrated circuits tend to have larger and higher-dimension design spaces to explore, making it prohibitively expensive to obtain physical characteristics of all possible designs using traditional synthesis tools.In this work, we propose a deep-learning-based synthesis predictor called SNS (SNS's not a Synthesizer), that predicts the area, power, and timing physical characteristics of a broad range of designs at two to three orders of magnitude faster than the Synopsys Design Compiler while providing on average a 0.4998 RRSE (root relative square error). We further evaluate SNS via two representative case studies, a general-purpose out-of-order CPU case study using RISC-V Boom open-source design and an accelerator case study using an in-house Chisel implementation of DianNao, to demonstrate the capabilities and validity of SNS. CCS CONCEPTS• Hardware → Integrated circuits; High-level and registertransfer level synthesis; • Computing methodologies → Neural networks.

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Section: Hardware Design Dataset Generationmentioning

confidence: 99%