Integrating physical level design and high level synthesis for simultaneous multi-cycle transient and multiple transient fault resiliency of application specific datapath processors

Particle swarm optimisation driven low cost single event transient fault secured design during architectural synthesis

“…Following are the novelties of the present paper: (a) Novel low cost optimised multi‐cycle and multi‐unit transient fault secured design based on user area‐delay constraints during fitness evaluation. (b) Novel particle swarm optimisation (PSO)‐based exploration methodology for high level synthesis for inclusive fitness assessment of a multi‐unit and multi‐cycle transient fault secured design solution. (c) The proposed approach obtains an area overhead reduction of 34.08% compared with [26], while simultaneously attaining a latency overhead reduction of 5.8% compared with [26]. …”

“… (a) The proposed approach presents low cost optimised multi‐cycle and multi‐unit transient fault security during HLS, while [26] only presents fault security methodology (with no optimisation in the secured design technique). (b) The proposed work integrates PSO DSE framework with the fault security approach to yield optimal design solution based on user constraints. However, [26] does not consider user constraint during generating optimised fault secured design solution. This resulted in expensive designs where the user cost budget is not met.…”

“…This resulted in expensive designs where the user cost budget is not met. Further, non‐optimised designs generated by [26] incur huge silicon overhead and delay expenditure. (c) Detailed sensitivity analysis of the PSO parameters on the quality of DSE results and exploration runtime is presented, which was not included in the seminal version.…”

“…Our work focuses on providing low cost optimised simultaneous fault security at behavioral (architecture) level against temporal and spatial effects of transient faults occurring due to single particle strike through physically aware high level synthesis methodology. The only work on similar topic is provided in authors' previous work [26] on non‐optimised transient fault security during HLS. However there is no effort (zero work) in prior art to provide concurrent low cost optimal solution to multi‐cycle transient and multiple transient fault security during HLS (note: the difference between proposed work and [26] is discussed earlier).…”

“…The only work on similar topic is provided in authors' previous work [26] on non‐optimised transient fault security during HLS. However there is no effort (zero work) in prior art to provide concurrent low cost optimal solution to multi‐cycle transient and multiple transient fault security during HLS (note: the difference between proposed work and [26] is discussed earlier).…”