Integrating SDL and VHDL for System-Level Hardware Design

Glunz, Wolfgang; Kruse, Thomas; Rössel, Torsten; Monjau, Dieter

doi:10.1016/b978-0-444-81641-2.50021-6

Cited by 35 publications

(10 citation statements)

References 10 publications

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“…Some projects have researched using this level for functional specification and synthesis, e.g [11], but they impose restrictions on the descriptions and communications in particular.…”

Section: Message Levelmentioning

confidence: 99%

A higher level system communication model for object-oriented specification and design of embedded systems

Svarstad

Ben-Fredj

Nicolescu

et al. 2001

Proceedings of the 2001 Conference on Asia South Pacific Design Automation - ASP-DAC '01

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Abstract-The design starting point for current embedded systems design is getting higher and higher on the abstraction level scale in order to meet the challenge of the increasing design gap. Up til now the state-of-the-art tools and methods have used as a highest abstraction of communication the send-receive over a channel, e.g. as in SDL and COSSAP. We introduce a novel higher level communication mechanism for system-level specification which has features supporting object-oriented descriptions and client-server type communication modelling as in CORBA. The communication primitives have been implemented as extensions to System-C, and simulation experiments have been performed.

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“…Some projects have researched using this level for functional specification and synthesis, e.g [11], but they impose restrictions on the descriptions and communications in particular.…”

Section: Message Levelmentioning

confidence: 99%

A higher level system communication model for object-oriented specification and design of embedded systems

Svarstad

Ben-Fredj

Nicolescu

et al. 2001

Proceedings of the 2001 Conference on Asia South Pacific Design Automation - ASP-DAC '01

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“…As reported in [2,7,9,19,20,21], SDL hardware descriptions are often translated into VHDL. This allows SDL to be used for high-level hardware description, coupled with common tools for hardware synthesis and further analysis.…”

Section: Introductionmentioning

confidence: 99%

Parallel and Distributed Processing

Boyanov¹

2000

Lecture Notes in Computer Science

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Digital hardware is treated as a collection of interacting parallel components. This permits the use of a standard formal technique for specification and analysis of circuit designs. The ANISEED method (Analysis In SDL Enhancing Electronic Design) is presented for specifying and analysing timing characteristics of hardware designs using SDL (Specification and Description Language). A signal carries a binary value and an optional time-stamp. Components and circuit designs are instances of block types in library packages. The library contains specifications of typical components in single/multi-bit and untimed/timed forms. Timing may be specified at an abstract, behavioural or structural level. Timing properties are investigated using an SDL simulator or validator. Consistency of temporal and functional aspects may be assessed between designs at different levels of detail. Timing characteristics of a design may also be inferred from validator traces. A variety of examples is used, ranging from a simple gate specification to realistic examples drawn from a standard hardware verification benchmark.

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“…This would yield complicated implementations that are too inef cient for our class of systems. The method in [6] supports only a subset of the speci cation language SDL. A generalpurpose hardware/software co-design method is described in [2] and [10], in which an SDL speci cation is gradually translated to C and/or VHDL code using a semi-automatic human-guided transformational approach.…”

Section: Existing Methods For System-level Synthesismentioning

confidence: 99%

“…Secondly, because the majority of behavioral descriptions by extended nite-state machines in SDL are translated directly to VHDL, except for communication behavior [10][7] [15]. Furthermore, only those SDL primitives and concepts are supported that allow a convenient transformation to VHDL [2] [6].…”

Section: Existing Methods For System-level Synthesismentioning

confidence: 99%

On the fundamental design gap in terabit per second packet switching

Verhappen

Putten²,

Voeten³

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools

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We discuss the gap we experience in an industrial design path of high-speed packet switches. As bandwidth demand exceeds progress in CMOS technology, system architects are forced to abandon familiar design solutions and make fundamental changes to their architectures at an increasingly faster pace. We investigate design methods to decrease the risk of such changes and to provide a structured and confident transition from conceptual system-level models to hardware descriptions. It appears that the design gap is caused by differences between language primitives and underlying concepts of system-level design languages and hardware description languages. We substantiate the need for expressive system-level modeling concepts and show that the gap is actually caused by a fundamental interpretation mismatch between models and descriptions. Based on a comparison of existing system-level synthesis methods with the interpretation gap, we propose to decrease the gap by using modeling patterns.

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Integrating SDL and VHDL for System-Level Hardware Design

Cited by 35 publications

References 10 publications

A higher level system communication model for object-oriented specification and design of embedded systems

A higher level system communication model for object-oriented specification and design of embedded systems

Parallel and Distributed Processing

On the fundamental design gap in terabit per second packet switching

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