Integration Challenges and Tradeoffs for Terascale Architectures

Static Task Mapping for Tiled Chip Multiprocessors with Multiple Voltage Islands

“…This led to the concept of tiled architecture, characterized by regular structures of homogeneous tiles, each one consisting of a processing core, a cache memory and a router. Further research in this area inspired designs with heterogeneous tiles, preserving the regularity of the structure, but introducing several classes of tiles [1], [7], [8]. Such systems may include some specialized processors (e.g., graphics, DSP) or different implementations of the same architecture (e.g., in-order/outof-order, multi-threading) with varied power-performance trade-offs.…”

An Efficient Way to Increase Performance by Using Low Power Reconfigurable Routers

“…Azimi et al [2] affirm that it is necessary to find a way to keep the off-die bandwidth manageable in system architectures with tradeoffs among cost, power, and performance. Moreover, in a hardware context, the system must offer flexibility with high-bandwidth, low-latency, and power-efficiency.…”

Cache Coherence Protocols for Many-Core CMPs

“…For example, the dual-core IBM Power6 (Le et al, 2007) and the eight-core Sun UltraSPARC T2 (Shah et al, 2007) have a relatively small number of cores, which are typically connected through a shared medium, i.e., a bus or a crossbar. However, CMP architectures that integrate tens of processor cores (usually known as many-core CMPs) are expected for the near future, after Intel recently unveiled the 80-core Polaris prototype (Azimi et al, 2007). Since the area required by a shared interconnect becomes impractical as the number of cores grows (Kumar et al, 2005), it seems that the processing cores of future CMPs will be connected by means of unordered point-to-point networks.…”

“…On the other hand, most CMP systems provide programmers with the intuitive sharedmemory model, which requires efficient support for cache coherence. Although a great deal of attention was devoted to scalable cache coherence protocols in the last decades in the context of shared-memory multiprocessors, the technological parameters and constraints entailed by many-core CMPs demand new solutions to the cache coherence problem (Bosschere et al, 2007;Azimi et al, 2007). In this chapter, we focus on three main design goals for cache coherence protocols aimed at being employed in many-core CMPs: performance, on-chip network traffic, and area requirements.…”

“…On the other hand, Directory reduces network traffic compared to Hammer by storing in a directory structure precise information about the private caches holding memory blocks. Unfor-6 www.intechopen.com tunately, the storage overhead that directories entail could become prohibitive for many-core CMPs (Azimi et al, 2007). Since neither the network traffic generated by Hammer nor the extra area required by Directory scale with the number of cores, a great deal of attention was paid in the past to address this traffic-area trade-off (Agarwal et al, 1988;Gupta et al, 1990;Chaiken et al, 1991;Mukherjee & Hill, 1994;Acacio et al, 2001).…”