2002
DOI: 10.1557/mrs2002.249
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Integration Challenges for CMP of Copper

Abstract: As the minimum feature size of microelectronic devices shrinks down to 130 nm, copper has been successfully adopted into logic applications.1–3 Copper requires damascene processing, which involves etching features into a dielectric substrate, filling the features with metal, and removing any excess metal. Therefore, chemical—mechanical planarization (CMP) is a key process in the final definition of the inlaid copper wires on a circuit. A second advance in the back-end processing of copper is the changing of th… Show more

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Cited by 16 publications
(8 citation statements)
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“…5 These problems can be mitigated by performing Cu and the barrier CMP at "low" pressures. 6,7 Because throughput cannot be sacrificed, this requires increasing the chemical activity of the CMP slurries so that soft surface films that can be easily removed at low polishing pressures are formed on the Cu film surface. A better understanding of the roles of various chemicals used in typical Cu CMP slurries along with the search for novel slurry additives is helpful to achieve this goal.…”
mentioning
confidence: 99%
“…5 These problems can be mitigated by performing Cu and the barrier CMP at "low" pressures. 6,7 Because throughput cannot be sacrificed, this requires increasing the chemical activity of the CMP slurries so that soft surface films that can be easily removed at low polishing pressures are formed on the Cu film surface. A better understanding of the roles of various chemicals used in typical Cu CMP slurries along with the search for novel slurry additives is helpful to achieve this goal.…”
mentioning
confidence: 99%
“…Chemical mechanical polishing (CMP) is employed as a viable method for planarizing the surface globally [1][2][3]. In a typical CMP process, a rotating wafer is pressed against a rotating polishing pad in the presence of slurry in between.…”
Section: Introductionmentioning
confidence: 99%
“…There is very little surface area between some of these high aspect ratio polymer mold features and the metal substrate, such that exposure to the etchant bath causes a loss of mold features and reduces the yield of usable MEMS components; wasting resources expended on x-ray lithography. Similar concerns regarding the adhesion of dielectric and barrier films arise in routine microelectronic fabrication procedures such as chemical-mechanical polishing 7,8 and packaging, [9][10][11][12] which involve exposure to wet environments and mechanical loading.…”
Section: Introductionmentioning
confidence: 99%