Integration of a high density Ta2O5 MIM capacitor following 3D damascene architecture compatible with copper interconnects

Thomas, M.; Farcy, A.; Gaillard, Nicolas; Perrot, C.; Gros-Jean, M.; Maťko, I.; Cordeau, M.; Saikaly, W.; Proust, M.; Caubet, P.; Deloffre, E.; Crémer, S.; Bruyère, S.; Chenevier, B.; Torrès, J.

doi:10.1016/j.mee.2006.09.027

Cited by 14 publications

(7 citation statements)

References 3 publications

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“…1 However, industry interest in alternate thin film high-κ dielectrics continued due to ever increasing capacitance density requirements. Many alternative high-κ insulators have been studied including Al 2 O 3 , 452,453 AlTiO 3 (ATO), [454][455] (Ba,Sr)TiO 3 (BST), [456][457][458][459] BiTaO, 460 (Bi,Ti)SiO 3 (BTSO), 461 HfO 2 , 462 HfSiO, 463 La 2 O 3 , 464 Sm 2 O 3 , 465 SrTiO 3 (STO), 457,[466][467][468][469] Ta 2 O 5 , 470,471 TiO 2 , 455,472 Y 2 O 3 , 473,474 and ZrO 2 . [475][476][477] The International Technology Roadmap for Semiconductors (ITRS) 2026 projections for MIM capacitors indicate a need for low equivalent oxide thickness (EOT) values near 1 nm while maintaining low leakage currents of 10 −8 A/cm 2 .…”

Section: Metal-insulator-metal Capacitors With High-κ Insulatorsmentioning

confidence: 99%

Review—Beyond the Highs and Lows: A Perspective on the Future of Dielectrics Research for Nanoelectronic Devices

Jenkins

Austin

Conley

et al. 2019

ECS J. Solid State Sci. Technol.

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High-dielectric constant (high-k) gate oxides and low-dielectric constant (low-k) interlayer dielectrics (ILD) have dominated the nanoelectronic materials research scene over the past two decades, but they have recently reached a state of maturity and perhaps the limits of their scaling. Based on this, there is a need for a systematic review summarizing not only the historic research and achievements on high-k and low-k dielectrics, but also emerging device applications as well as an outlook of future challenges. We begin by first reviewing the factors that drove the emergence of low-k and high-k materials in nanoelectronics as ILD and gate dielectric materials, respectively, and the challenges and limits these materials ultimately approached in terms of permittivity scaling. We then illustrate that gate dielectric and ILD applications represent just a small fraction of the numerous dielectrics utilized in present day nanoelectronic products where permittivity scaling is now being increasingly demanded for materials such as dielectric spacers, trench isolation, and etch stopping layers. We conclude by examining the numerous new applications for dielectric materials that are emerging as the semiconductor industry transitions to novel patterning schemes, prepares for life post CMOS scaling, and explores ways to natively embed device functionality in the metal interconnect. For the former, we specifically examine the “colorful” requirements for the various enabling dielectric hardmask and spacer materials utilized in pitch division-multi-pattern processes and then discuss the role that selective area deposition of dielectrics and metals could play in reducing the complexity of such patterning processes. For the latter, we review the use of both high-k and low-k dielectrics in various metal-insulator-metal (MIM) structures as Fermi level de-pinning layers, tunnel diodes, and back-end-of-line (BEOL) compatible capacitive and resistive switching random access memory (ReRAM) elements. We further examine how dielectrics can hinder or aid new forms of computing such as quantum and neuromorphic in reaching their full potential. In conclusion, we find that while the field of dielectrics has a long history, it remains vibrant with numerous exciting new and old research vectors awaiting further exploration.

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Section: Metal-insulator-metal Capacitors With High-κ Insulatorsmentioning

confidence: 99%

Review—Beyond the Highs and Lows: A Perspective on the Future of Dielectrics Research for Nanoelectronic Devices

Jenkins

Austin

Conley

et al. 2019

ECS J. Solid State Sci. Technol.

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“…Other applications where high-k dielectrics are interesting include integrated capacitors for decoupling, RF Integrated Circuits (RFICs), analog/mixed signal circuits, or DRAM applications. Medium-k dielectrics such as Ta [2,3,4]with dielectric constants in the range of 10-20 (about 80 for TiO 2 ) are the most widely used because they can be deposited with Chemical Vapour Deposition (CVD) techniques and thermodynamically they show thermal stability with silicon. Very high-k dielectrics generally presents a perovskite structure, such as SrTiO 3 [5], BaTiO 3 , BaSrTiO 3 , PbZrTiO 3 [6], PbLaZrTiO 3 [7], which leads to dielectric constants typically above 100 and in some cases around or above 1000.…”

Section: ) Dielectricsmentioning

confidence: 99%

High-Density 3-D Capacitors for Power Systems On-Chip: Evaluation of a Technology Based on Silicon Submicrometer Pore Arrays Formed by Electrochemical Etching

Brunet

Kleimann

2013

IEEE Trans. Power Electron.

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This paper presents the state of the art technologies currently used to produce high density integrated capacitors for power systems on-chip applications. The use of high-k dielectrics and 3D patterning of silicon for reaching high specific capacitance is reviewed. Integrating capacitors monolithically on the active chip or in package of power systems is discussed and solutions are proposed for minimising series resistance and achieving a high level of integration. A technology based on nanolithography and silicon electrochemical etching is then detailed. It is shown that capacitance densities of up to 700 nF/mm² can be obtained with a submicrometer pores array in a relatively limited thickness. The advantages and disadvantages of further decreasing the pore size to nanosize pores (below 100 nm) are discussed.

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“…High capacitance densities may be reached by decreasing the dielectric thickness, increasing the surface area or by using a dielectric with high permittivity (k). High-k materials have been widely investigated in microelectronics as a replacement for silicon oxide in transistors and they appear as well for integrated capacitors: in particular Ta 2 O 5 [22,23] Al 2 O 3 [22], STO [24], BST, PZT [25]. However, in planar configuration, the capacitance density for 10 V applications is rarely higher than 10 nF/mm² [26].…”

Section: B Capacitor Designmentioning

confidence: 99%

Design and realization of highly integrated isolated DC/DC micro-converter

Deleage¹,

Crébier²,

Brunet

et al. 2009

2009 IEEE Energy Conversion Congress and Exposition

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This paper deals with the design and the realization of an integrated isolated HF DC to DC converter for low voltage and low power conditioning applications (3,3V and 1W). It is based on the 3D integration of several elementary silicon dies in which have been integrated essential components such as the inverter, the rectifier, the HF transformer, the input and output capacitors and the output inductor. The paper deals with the silicon integration of all these elements, the presentation of our work being related with the state of the art. Then it focuses on a global estimation of the whole converter functional performances at 1MHz switching frequency. Practical but partial implementation was carried out. The inverter and the rectifier are designed in CMOS technology (Austria Micro Systems 0.35µm) and have been optimized to operate at high frequency (1MHz) in order to reduce the size of passive devices. We have integrated monolithically all is necessary for this function. The transformer as well as the inductor and the capacitors are also integrated on separate silicon dies. Their integration is discussed as well as their design and practical characterization. Based on all these pieces, the overall converter efficiency is estimated in simulation based on practical characterizations. It appears that correct efficiency with a reasonable silicon surface and volume can be reached.

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Integration of a high density Ta2O5 MIM capacitor following 3D damascene architecture compatible with copper interconnects

Cited by 14 publications

References 3 publications

Review—Beyond the Highs and Lows: A Perspective on the Future of Dielectrics Research for Nanoelectronic Devices

Review—Beyond the Highs and Lows: A Perspective on the Future of Dielectrics Research for Nanoelectronic Devices

High-Density 3-D Capacitors for Power Systems On-Chip: Evaluation of a Technology Based on Silicon Submicrometer Pore Arrays Formed by Electrochemical Etching

Design and realization of highly integrated isolated DC/DC micro-converter

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