Integration of Flowfill and Forcefill for cost-effective via applications

Abstract

This paper reviews work to integrate Flowfihl® planarizing dielectric with Forcefihl® aluminum plug in a O.5/O.35im CMOS design. Work to reduce dielectric cracking by modifying the stress of the IMD material is described. The paper discusses liner choice for the Forcefill® interconnect and how it can influence lithography accuracy, line resistance and electromigration. The use of via chain resistance as a test to determine the degree of metal hole-fill is described.