Integration of IC Industry Feature Sizes with University Back-End-of-Line Post Processing: Example Using a Phase-Change Memory Test Chip

Regner, Jennifer; Balasubramanian, M.; Cook, Beth; Li, Yingting; Kassayebetre, Hiwot; Sharma, Anshika; Baker, R. Jacob; Campbell, Kristy A.

doi:10.1109/wmed.2009.4816141

Cited by 3 publications

(2 citation statements)

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“…The BEOL mask levels, process flow, and fabrication were completed at Boise State. The fabrication process used the BEOL process for memristor device integration with CMOS that has previously been established [42].…”

Section: Beol Development For Asu Ic Test Chipmentioning

confidence: 99%

Reconfigurable Electronics and Non-Volatile Memory Research

Campbell¹

2015

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Section: Beol Development For Asu Ic Test Chipmentioning

confidence: 99%

Reconfigurable Electronics and Non-Volatile Memory Research

Campbell¹

2015

Self Cite

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“…These differences also enable the device used in this work to withstand higher fabrication (at least 300°C) and operating temperatures (operation at 150°C is routinely performed). Additionally, this device can be integrated into a back-end-of-line (BEOL) CMOS process (Regner et al, 2009) making it compatible with CMOS architectures (Serrano-Gotarredona et al, 2013b). …”

Section: Introductionmentioning

confidence: 99%

Pulse Shape and Timing Dependence on the Spike-Timing Dependent Plasticity Response of Ion-Conducting Memristors as Synapses

Campbell

Drake

Smith

2016

Front. Bioeng. Biotechnol.

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Ion-conducting memristors comprised of the layered materials Ge2Se3/SnSe/Ag are promising candidates for neuromorphic computing applications. Here, the spike-timing dependent plasticity (STDP) application is demonstrated for the first time with a single memristor type operating as a synapse over a timescale of 10 orders of magnitude, from nanoseconds through seconds. This large dynamic range allows the memristors to be useful in applications that require slow biological times, as well as fast times such as needed in neuromorphic computing, thus allowing multiple functions in one design for one memristor type—a “one size fits all” approach. This work also investigated the effects of varying the spike pulse shapes on the STDP response of the memristors. These results showed that small changes in the pre- and postsynaptic pulse shape can have a significant impact on the STDP. These results may provide circuit designers with insights into how pulse shape affects the actual memristor STDP response and aid them in the design of neuromorphic circuits and systems that can take advantage of certain features in the memristor STDP response that are programmable via the pre- and postsynaptic pulse shapes. In addition, the energy requirement per memristor is approximated based on the pulse shape and timing responses. The energy requirement estimated per memristor operating on slower biological timescales (milliseconds to seconds) is larger (nanojoules range), as expected, than the faster (nanoseconds) operating times (~0.1 pJ in some cases). Lastly, the memristors responded in a similar manner under normal STDP conditions (pre- and post-spikes applied to opposite memristor terminals) as they did to the case where a waveform corresponding to the difference between pre- and post-spikes was applied to only one electrode, with the other electrode held at ground potential. By applying the difference signal to only one terminal, testing of the memristor in various applications can be achieved with a simplified test set-up, and thus be easier to accomplish in most laboratories.

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The Self-directed Channel Memristor: Operational Dependence on the Metal-Chalcogenide Layer

Campbell

2019

Handbook of Memristor Networks

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Integration of IC Industry Feature Sizes with University Back-End-of-Line Post Processing: Example Using a Phase-Change Memory Test Chip

Cited by 3 publications

References 9 publications

Reconfigurable Electronics and Non-Volatile Memory Research

Reconfigurable Electronics and Non-Volatile Memory Research

Pulse Shape and Timing Dependence on the Spike-Timing Dependent Plasticity Response of Ion-Conducting Memristors as Synapses

The Self-directed Channel Memristor: Operational Dependence on the Metal-Chalcogenide Layer

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