Integration of InP and InGaAs on 300 mm Si Wafers Using Chemical Mechanical Planarization

Abstract

Integration of III-V high mobility channel materials in complementary metal oxide semiconductors (CMOS) and III-V photonic materials for integrated light sources on Si substrates requires low defect density III-V buffer layers in order to enable epitaxial growth of high crystal quality active layers. For the fabrication of In 0.53 Ga 0.47 As n-channel MOSFET on Si, a lattice matched InP buffer layer is one of the most effective approaches when used in combination with the aspect ratio trapping technique, an integration method known for reducing the density of defects formed during relaxation of strain induced by the lattice mismatch between InP and Si. The InP buffer should be planarized in order to improve thickness uniformity and roughness before subsequent deposition of active layers. In this work we discuss the development of InP planarization on 300mm Si wafers and investigate slurry composition effects on the final oxide loss and condition of the InP surface. To further explore viability of this approach we deposited an epitaxial In 0.53 Ga 0.47 As n-MOS channel layer on top of the planarized InP buffer.

Review—Post-Chemical Mechanical Planarization Cleaning Technology

“…141,143 With the miniaturization of metal oxide semiconductor devices (MOS) to less than 10 nm node, semiconductor metal alloy indium gallium arsenide (InGaAs) has been introduced due to its epitaxial mixing with Si. 146,147 However, CMP leaves various contaminants, including residues of abrasive silica particles on the surface of InGaAs. 123 These contaminants could not be effectively removed by the conventional cleaning solutions comprising of HF and NH 4 OH.…”

Thin Ferrite Wafer Uniformly Polished with Magnetic Attraction Method

“…CMP is an ultra-precision mechanical technology that is widely used for polishing integrated circuit chips 1,2 and other materials. It can be used for nano-level polishing of many hard and brittle materials, including silicon, 1,2 glass, 3,4 ceramics, 5 sapphire.…”

Post-CMP Cleaning of InGaAs Surface for the Removal of Nanoparticle Contaminants for Sub-10nm Device Applications

“…[3][4][5][6] InGaAs is a III-V material suitable for sub-10nm logic devices due to its epitaxial matching with Si. 7,8 In order to utilize InGaAs in logic devices, one or more chemicalmechanical polishing (CMP) steps are needed to obtain a planarized surface. [8][9][10] Residual contamination from silica slurry is found on In-GaAs surfaces after CMP process necessitating a post-CMP cleaning step.…”

“…7,8 In order to utilize InGaAs in logic devices, one or more chemicalmechanical polishing (CMP) steps are needed to obtain a planarized surface. [8][9][10] Residual contamination from silica slurry is found on In-GaAs surfaces after CMP process necessitating a post-CMP cleaning step. 11 Conventional cleaning solutions based on NH 4 OH and DHF are limited to the surface etching and cleaning of InGaAs itself, 12,13 so novel processes are required to remove contaminant particles and oxide from the substrate surface.…”