Integration of Learning Techniques into Incremental Satisfiability for Efficient Path-Delay Fault Test Generation

Chandrasekar, Kameshwar; Hsiao, Michael S.

doi:10.1109/date.2005.187

Cited by 13 publications

(8 citation statements)

References 13 publications

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“…Majority of the existing approaches exploit incremental satisfiability to improve the test generation time involving only one property with different bounds. There are very few approaches such as [13] where both static and dynamic learning are used across test generation instances for path-delay fault model by dynamically excluding the untestable path during test generation. Since the learning is employed across all test scenarios without efficient clustering methods, the improvement in test generation time is small (6 % on average) and has a wide variation (−7 to 27 %) on different ISCAS circuits.…”

Section: Related Workmentioning

confidence: 99%

Property Clustering and Learning Techniques

Chen

Qin

Koo

et al. 2012

System-Level Validation

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Section: Related Workmentioning

confidence: 99%

Property Clustering and Learning Techniques

Chen

Qin

Koo

et al. 2012

System-Level Validation

View full text Add to dashboard Cite

“…Majority of the existing approaches exploit incremental satisfiability to improve the test generation time involving only one property with different bounds. There are very few approaches such as [18] where both static and dynamic learning is used across test generation instances for path-delay fault model by dynamically excluding the untestable path during the test generation. Since the learning is employed across all test scenarios without efficient clustering methods, the improvement in test generation time is small (6% on average) and have a wide variation (−7% to 27%) on different ISCAS circuits.…”

Section: Related Workmentioning

confidence: 99%

Functional Test Generation Using Efficient Property Clustering and Learning Techniques

Chen

Mishra

2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Functional verification is one of the major bottlenecks in system-on-chip design due to the combined effects of increasing complexity and lack of automated techniques for generating efficient tests. Several promising ideas using bounded model checking are proposed over the years to efficiently generate counterexamples (tests). The existing researchers have used incremental satisfiability to improve the counterexample generation, involving only one property by sharing knowledge across instances of the same property with incremental bounds. In this paper, we present a framework that can efficiently reduce the overall test generation time by exploiting the similarity among different properties. This paper makes two primary contributions: 1) it proposes novel methods to cluster similar properties; and 2) it develops efficient learning techniques that can significantly reduce the overall test generation time for the properties in a cluster by sharing knowledge across similar test generation instances. Our experimental results using both software and hardware benchmarks demonstrate that our approach can drastically reduce (on average three to five times) the overall test generation time compared to existing methods.

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“…The reuse of learned information has been shown to improve the performance in computer aided design, for example in formal verification [20] or automatic test pattern generation [21], [22], [23]. In particular, SAT solvers store learned information in terms of conflict clauses that are easily accessible.…”

Section: Clause Reusementioning

confidence: 99%

Computing bounds for fault tolerance using formal techniques

Fey

Sülflow

Drechsler

2009

Proceedings of the 46th Annual Design Automation Conference

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Abstract-While facing continuously shrinking feature sizes, the demand for fault tolerance in digital circuits increases. Numerous approaches to achieve robustness on the design side have been presented. But ensuring that the fault tolerance is really achieved is a tough verification problem.Here, we propose a formal model and an effective algorithm to formally prove the robustness of a digital circuit. The proposed model uses a fixed bound in time to cope with the complexity of the sequential equivalence check. The result is a lower and an upper bound on the robustness. The underlying algorithm and techniques to improve the efficiency are presented. In the experiments the method was evaluated on circuits with different fault detection mechanisms.

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Integration of Learning Techniques into Incremental Satisfiability for Efficient Path-Delay Fault Test Generation

Abstract: In recent years, several Electronic Design Automation (EDA)

Cited by 13 publications

References 13 publications

Property Clustering and Learning Techniques

Property Clustering and Learning Techniques

Functional Test Generation Using Efficient Property Clustering and Learning Techniques

Computing bounds for fault tolerance using formal techniques

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