Integration of SPAD in 28nm FDSOI CMOS technology

Dark Count Rate Modeling in Single-Photon Avalanche Diodes

“…SPAD fabrication in CMOS process enables a high integration density with the possibility to combine the detector and the driving electronics on the same chip [2]. The CMOS technology is mature and many technology nodes have been integrated with success, from 0.8 µm to an advanced 40 nm technology [3] and 28 nm using fully depleted silicon on insulator (FDSOI) CMOS technology [4]. Analysis and simulation are fundamental steps in CMOS process work-flow, to study and predict performance parameters as design, fabrication and characterization are time consuming and costly.…”

Lowering the Dark Count Rate of SPAD Implemented in CMOS FDSOI Technology

“…In [3], authors presented the first experimental results on a SPAD fabricated in STMicroelectronics' CMOS FDSOI 28nm technology without any design rule violation nor process customization. The diode was implemented with P-well and deep N-well layers which are conventionally intended for transistor back-biasing.…”

“…It is consistent with TCAD simulation results. However, it was not possible to acquire additional experimental data at higher biasing voltages, since the DCR is adversely impacted by afterpulsing events for such operating points [3].…”

“…Then the top die holds the SPAD array with a backside illumination (BSI) and the CMOS bottom die contains all the signal processing, quenching etc. An alternative way is explored based on advanced CMOS Fully Depleted Silicon-On-Insulator (FDSOI) technology [3]. The SPAD is implemented below the buried oxide (BOX) while the transistors are placed in the usual thin silicon layer, as shown in Fig.…”

“…Schematic of SPAD implementation in CMOS FDSOI technology below the buried oxide (half-cell with axial symmetry), scales are not respected[3] …”