Intel OpenVINO Toolkit for Computer Vision: Object Detection and Semantic Segmentation

Zunin, V.V.

doi:10.1109/rusautocon52004.2021.9537452

Cited by 15 publications

(6 citation statements)

References 15 publications

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“…In addition to designing the computational architecture, the MATLAB code can be automatically converted to RTL code and run on FPGAs [ 29 ]. There are also some implementations developed using HLS [ 30 , 31 ] and other tools [ 32 ]. These methods may speed up development, but they are not specifically optimized for performance.…”

Section: Related Workmentioning

confidence: 99%

An Image Histogram Equalization Acceleration Method for Field-Programmable Gate Arrays Based on a Two-Dimensional Configurable Pipeline

Wang,

Liu,

et al. 2024

Sensors

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New artificial intelligence scenarios, such as high-precision online industrial detection, unmanned driving, etc., are constantly emerging and have resulted in an increasing demand for real-time image processing with high frame rates and low power consumption. Histogram equalization (HE) is a very effective and commonly used image preprocessing algorithm designed to improve the quality of image processing results. However, most existing HE acceleration methods, whether run on general-purpose CPUs or dedicated embedded systems, require further improvement in their frame rate to meet the needs of more complex scenarios. In this paper, we propose an HE acceleration method for FPGAs based on a two-dimensional configurable pipeline architecture. We first optimize the parallelizability of HE with a fully configurable two-dimensional pipeline architecture according to the principle of adapting the algorithm to the hardware, where one dimension can compute the cumulative histogram in parallel and the other dimension can process multiple inputs simultaneously. This optimization also helps in the construction of a simple architecture that achieves a higher frequency when implementing HE on FPGAs, which consist of configurable input units, calculation units, and output units. Finally, we optimize the pipeline and critical path of the calculation units. In the experiments, we deploy the optimized HE on a VCU118 test board and achieve a maximum frequency of 891 MHz (which is up to 22.6 times more acceleration than CPU implementations), as well as a frame rate of 1899 frames per second for 1080p images.

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Section: Related Workmentioning

confidence: 99%

An Image Histogram Equalization Acceleration Method for Field-Programmable Gate Arrays Based on a Two-Dimensional Configurable Pipeline

Wang,

Liu,

et al. 2024

Sensors

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“…Collaboration can lead to faster development and adoption of new ML techniques and applications. Other open-source ML inference accelerators, such as Intel's OpenVINO and Xilinx's Deep Learning Processor, are available alongside VTA [17] [18]. These accelerators provide developers with a variety of options for building and optimizing machine learning systems.…”

Section: Open-source ML Inference Acceleratorsmentioning

confidence: 99%

Design optimization for high-performance computing using FPGA

Isik

Inadagbo²,

Aktaş

2023

Preprint

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Reconfigurable architectures like Field Programmable Gate Arrays (FPGAs) have been used for accelerating computations in several domains because of their unique combination of flexibility, performance, and power efficiency. However, FPGAs have not been widely used for high-performance computing, primarily because of their programming complexity and difficulties in optimizing performance. We optimize Tensil AI's open-source inference accelerator for maximum performance using ResNet20 trained on CIFAR in this paper in order to gain insight into the use of FPGAs for high-performance computing. In this paper, we show how improving hardware design, using Xilinx Ultra RAM, and using advanced compiler strategies can lead to improved inference performance. We also demonstrate that running the CIFAR test data set shows very little accuracy drop when rounding down from the original 32-bit floating point. The heterogeneous computing model in our platform allows us to achieve a frame rate of 293.58 frames per second (FPS) and a \%90 accuracy on a ResNet20 trained using CIFAR. The experimental results show that the proposed accelerator achieves a throughput of 21.12 Giga-Operations Per Second (GOP/s) with a 5.21 W on-chip power consumption at 100 MHz. The comparison results with off-the-shelf devices and recent state-of-the-art implementations illustrate that the proposed accelerator has obvious advantages in terms of energy efficiency.

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“…The availability of open-source tools and platforms allows developers to collaborate to develop better ML inference solutions. In addition to VTA [34] [31], other open-source ML inference accelerators are available, such as Intel's OpenVINO and Xilinx's Deep Learning Processor. These accelerators provide a variety of options for the development and optimization of machine learning systems.…”

Section: Open-source ML Inference Acceleratorsmentioning

confidence: 99%