Intellectual property protection by watermarking combinational logic synthesis solutions

Kirovski, D.; Hwang, Yean-Yow; Potkonjak, M.; Cong, J.

doi:10.1109/iccad.1998.742872

Cited by 25 publications

(43 citation statements)

References 3 publications

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“…The essence of their approach is to introduce watermark-related additional constraints into the input of a black-box design tool such that the design will be rather unique and the embedded watermark can be revealed as proof of authorship. This approach is generic and has been applied to various stages of the VLSI design process, from behavioral and logic synthesis to standard cell place and route algorithms, to FPGA designs [7,8,9,10,11,14].…”

Section: Vlsi Design Ip Protectionsmentioning

confidence: 99%

Soft IP Protection: Watermarking HDL Codes

Lin

Pari

2004

Lecture Notes in Computer Science

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Abstract. Intellectual property (IP) reuse based design is one of the most promising techniques to close the so-called design productivity gap. To facilitate better IP reuse, it is desirable to have IPs exchanged in the soft form such as hardware description language (HDL) source codes. However, soft IPs have higher protection requirements than hard IPs and most existing IP protection techniques are not applicable to soft IPs. In this paper, we describe the basic requirements, make the necessary assumptions, and propose several practical schemes for HDL code protection. We protect the HDL codes by hiding author's signature also called as watermarking, similar to the idea for hard IP and multimedia data protection. But the new challenge is how to embed watermark into HDL source codes, which must be properly documented and synthesizable for reuse. We leverage the unique feature of Verilog HDL design to develop several watermarking techniques. These techniques can protect both new and existing Verilog designs. We watermark SCU-RTL & ISCAS benchmark Verilog circuits, as well as a MP3 decoder. Both original and watermarked designs are implemented on ASICs & FPGAs. The results show that the proposed techniques survive the commercial synthesis tools and cause little design overhead in terms of area/resources, delay and power.

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Section: Vlsi Design Ip Protectionsmentioning

confidence: 99%

Soft IP Protection: Watermarking HDL Codes

Lin

Pari

2004

Lecture Notes in Computer Science

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“…Since design watermarking is an effective and efficient method for protecting the rights of IP owners, a number of interesting and efficient watermarking methods were proposed in the literature [1], [2], [3], [4], [5], [6], [7], [8]. Watermarking can be done at the different steps during synthesis and layout processes.…”

Section: Introductionmentioning

confidence: 99%

Provably secure obfuscation of diverse watermarks for sequential circuits

Koushanfar

Alkabani

2010

2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)

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Abstract-This paper presents a provably secure method for embedding multiple watermarks in sequential designs. A number of different watermarks signed with the IP owner's secret key from a public key cryptography system are generated. The owner's watermarks are then dissembled into the states and transitions of the original sequential design. Hiding the multiple watermarks in the states and transitions is shown to be an instance of obfuscating a multi-point function with a generalized output. We draw on the theoretical cryptographic results of provable obfuscation of this function family to build a secure sequential multi-watermark system by construction. An iterative synthesis method for integrating the collection of watermarks to the original design is introduced. Analysis of watermark properties and the attack resiliency of the new multiple watermarking construction is presented. Experimental evaluations on benchmark circuits demonstrate practicality and low overhead of the new provably secure multiple watermarks construction method.

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“…• exploit the scan-chain [5], • preserve nets during logic synthesis [6], • place constraints for CLBs in odd/even rows [7], or • route constraints with unusual routing resources [7]. The major drawback of these approaches are the limitations of the verification possibilities of the watermarked core.…”

Section: Introductionmentioning

confidence: 99%

Power Signature Watermarking of IP Cores for FPGAs

Ziener

Teich

2007

J Sign Process Syst Sign Image

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Abstract-In this paper, we introduce a new method for watermarking of IP cores for FPGA architectures where the signature (watermark) is detected at the power supply pins of the FPGA. This is the first watermarking method where the signature is extracted in this way. We are able to sign IP cores at the netlist as well as the bitfile level, so a wide spectrum of cores can be protected. In principle, the proposed power watermarking method works for all kinds of FPGAs. For Xilinx FPGAs, we demonstrate in detail that we can integrate the watermarking algorithms and the signature into the functionality of the watermarked core. So it is very hard to remove the watermark without destroying the core. Furthermore, we introduce a detection algorithm which can decode the signature from a voltage trace with high reliability. Additionally, two enhanced robustness algorithms are introduced which improve the detection probability in case of considerable noise sources. Using these techniques, it is possible to decode the signature even if other cores operate on the same device at the same time.

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Intellectual property protection by watermarking combinational logic synthesis solutions

Cited by 25 publications

References 3 publications

Soft IP Protection: Watermarking HDL Codes

Soft IP Protection: Watermarking HDL Codes

Provably secure obfuscation of diverse watermarks for sequential circuits

Power Signature Watermarking of IP Cores for FPGAs

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