Intelligent Adaptation of Hardware Knobs for Improving Performance and Power Consumption

Abstract

Current microprocessors include several knobs to modify the hardware behavior in order to improve performance, power, and energy under different workload demands. An impractical and time consuming offline profiling is needed to evaluate the design space to find the optimal knob configuration. Different knobs are typically configured in a decoupled manner to avoid the time-consuming offline profiling process. This can often lead to underperforming configurations and conflicting decisions that jeopardize system power-performance efficiency. Thus, a dynamic management of the different hardware knobs is necessary to find the knob configuration that maximizes system power-performance efficiency without the burden of offline profiling. In this paper, we propose libPRISM, an infrastructure that enables the transparent management of multiple hardware knobs in order to adapt the system to the evolving demands of hardware resources in different workloads. libPRISM can minimize execution time, energy-delay product or power consumption by dynamically managing the SMT level, the data prefetcher, and the DVFS hardware knobs. Overall, the proposed solutions increase performance up to 130% (16.9% on average), reduce energy-delay product up to 80%, and reduce power consumption up to 33% depending on the target metric compared to the default knob configuration of the system.

DeepP: Deep Learning Multi-Program Prefetch Configuration for the IBM POWER 8

“…Some recent research [12], [13], [14], [15], [19], [20] has focused on heuristic-based solutions with the aim of achieving the best performance from the prefetching capabilities of commercial machines. All these works focus on IBM POWER processors, whose prefetcher is much more powerful and complex, and further performance gains are expected.…”

“…In [20], a spatial bit-pattern prefetcher is proposed, which uses memory bandwidth utilization to adjust prefetch aggressiveness on Intel Skylake processors, its performance improvements are directly related with the available memory bandwidth. In [12], authors propose a strategy to select at run-time the best prefetch setting with the goal of enhancing the performance of parallel workloads when running a single application on an IBM POWER8 processor. In contrast, the strategy proposed in [13] is aimed at selecting the best prefetch setting for single-threaded multi-program workloads in the IBM POWER7 processor.…”

“…Recent work [17], [12], [15] found that depth and urgency are the fields that impact on performance the most The former configures the level of the prefetch depth and is related to the number of cache lines that are brought into the on-chip caches. Urgency indicates how quickly this depth can be reached.…”

“…Recent research has focused on dynamically selecting the best prefetch configuration for the running workload at run-time. Some works have concentrated on parallel workloads [12], [13], [14] and other approaches target multi-program single-threaded workloads [15] which is particularly complex because each application has different memory characteristics and prefetch requirements.…”

Smart resource allocation of concurrent execution of parallel applications

“…Then, it is proposed a mathematical model and a packing algorithm to optimize the mapping of applications compute nodes to I/O nodes. Ortega et al 35 propose libPRISM, an infrastructure that enables the transparent management of multiple hardware knobs (e.g., simultaneously multi‐threading level, data prefetcher, and DVFS configuration) to optimize the performance and power consumption of OpenMP parallel applications.…”