Intelligent Fault-Prediction Assisted Self-Healing for Embryonic Hardware

Khalil, Kasem; Eldash, Omar; Kumar, Ashok; Bayoumi, Magdy

doi:10.1109/tbcas.2020.2995784

Cited by 36 publications

(9 citation statements)

References 35 publications

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“…Since the convolution kernel is mostly linear, it is more suitable for learning the potential features of linear separability. For the diagnosis of rolling bearing vibration signals, the frequency component of the signal in the frequency domain is more important than the performance in the time domain [22]. Therefore, an improvement in the traditional convolution kernel can make the CNN model more suitable for vibration signals.…”

Section: A Convolution Layermentioning

confidence: 99%

Research on a Rolling Bearing Fault Detection Method With Wavelet Convolution Deep Transfer Learning

2021

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Section: A Convolution Layermentioning

confidence: 99%

Research on a Rolling Bearing Fault Detection Method With Wavelet Convolution Deep Transfer Learning

2021

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“…In actual use, the errors of memory in online occur due to various causes such as the aging of elements [36], the failure of modules in memory [37]. When correcting data of the memory in online, regardless of the cause of the error, it is recognized as an error in the memory cell and corrected by ECC.…”

Section: Reliabilitymentioning

confidence: 99%

“…It is measured for estimating the average lifetime of a chip. The MTTF is obtained by integrating the reliability function with time [32], [37]. Calculating the MTTF, FGPM is 624,946 hours, HA is 514,556 hours, OA is 445,134 hours, and the proposed method is 574,672 hours.…”

Section: Reliabilitymentioning

confidence: 99%

ECC-Aware Fast and Reliable Pattern Matching Redundancy Analysis for Highly Reliable Memory

Han

Lee

et al. 2021

IEEE Access

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Advanced capacity and density of memory have resulted in an increase in the probability of memory faults. The in-memory Error Correction Code (ECC), which solves this problem, is a widely used technology to improve the yield of highly integrated memory. However, the use of in-memory ECC causes problems that have not been considered in memory repair algorithms. Redundancy analysis is effective for repairing memory with redundant memory and in-memory ECC. In this paper, an ECC-aware fast and reliable pattern matching redundancy analysis algorithm for memory using both spare memory and in-memory ECC is proposed. This algorithm simplifies large-scale fault groups using in-memory ECC and includes an early termination method that can determine whether a memory that cannot be repaired with line spares can be repaired considering in-memory ECC. Experimental results show that the proposed pattern matching redundancy analysis algorithm achieves a similar yield but 14.6% less RA time and 8.6 times higher reliability compared to the existing redundancy analysis algorithms.

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“…Machine learning is significant for solving complex issues in different domains [1,2]. Long Short-Term Memory (LSTM) is a variant of Recurrent Neural Network (RNN) used to process long-term dependencies in data sequence and widely used in applications like speech recognition [3], Natural Language Processing (NLP) [4], fault prediction [5], and language translation [6], audio/video signal analysis, etc. Existing FPGA implementations of LSTM hardware architectures suffer from computationally intensive operations on large input sequences and exhibit high power consumption.…”

Section: Introductionmentioning

confidence: 99%

A Reversible-Logic Based Architecture for Long Short-Term Memory (LSTM) Network

Khalil

Dey

Kumar

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Any sequential learning task relies on the idea of connecting previous time-stamp information to the immediate present time-stamp task to predict the future. The underlying challenge is to understand the hidden patterns in the sequence by means of analyzing short-and long-term dependencies and temporal differences. Recurrent Neural Networks (RNNs) and their variants, such as Long Short-Term Memory (LSTM) are widely used in problem domains like speech recognition, Natural Language Processing (NLP), fault prediction, and language translation modeling over the past few years. Higher accuracy demands complex LSTM network models which lead to high computational cost, area overhead, and excessive power consumption. Reversible logic circuit synthesis, in the context of ideally Zero heat dissipation, has emerged as a new research paradigm for low power circuit designs. In this paper, we have proposed a novel design of LSTM architecture using reversible logic gates. To the best of our knowledge, the proposed approach is the first attempt to implement a complete feedforward LSTM circuit using only reversible logic gates. The hardware implementation of the proposed method is presented using VHDL and Altera Arria10 GX FPGA. The comparative analysis demonstrates that the proposed approach has achieved an approximately 17% reduction in overall power dissipation compared to traditional networks. The proposed approach also has better scalability than the classical design approach.

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Intelligent Fault-Prediction Assisted Self-Healing for Embryonic Hardware

Cited by 36 publications

References 35 publications

Research on a Rolling Bearing Fault Detection Method With Wavelet Convolution Deep Transfer Learning

Research on a Rolling Bearing Fault Detection Method With Wavelet Convolution Deep Transfer Learning

ECC-Aware Fast and Reliable Pattern Matching Redundancy Analysis for Highly Reliable Memory

A Reversible-Logic Based Architecture for Long Short-Term Memory (LSTM) Network

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