Inter Symbol Interference Correction Based on Zero-forcing Equalization for Time Interleaved Photonic Analog to Digital Converters

Jin, Zhengtao; Wu, Guiling; Wang, Cheng; Chen, Jianping

doi:10.1364/cleo_si.2018.sth3b.5

Cited by 4 publications

(1 citation statement)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Due to the parallel interface facing serious problems such as crosstalk and noise (SSN) in high-speed data transmission, the high-speed serial interface has become the mainstream transmission method. Today's high-speed serial link usually uses SerDes (Serializer and Deserializer) technology [1,2], That is, high-speed serial data for data transmission between chips or boards.…”

Section: Introductionmentioning

confidence: 99%

A Low BER DB-PAM4 Adaptive Equalizer for Large Channel Loss in Wireline Receivers

Wang

Lai²,

Lyu³

et al. 2022

Electronics

View full text Add to dashboard Cite

A high-speed serial interface is the core IP of a high-performance computer, data center and interconnection network; its bandwidth and bit error performance restrict the development of the system. With the evolution of high-speed serial interface line rates from 56 G to 112 G in high-end information systems, their bit errors increase sharply, limiting system performance. In order to solve the high-bit-error problem of the 112 Gb/s high-speed serial interface, this paper proposes a low-error Duo-binary PAM4 (DB-PAM) receive equalization technology. This technology utilizes the Duo-binary (DB) signal in which the channel and the transceiving equalizer work together to realize the low-error reception of the 112 Gb/s signal in the high-attenuation channel. To solve the problem of difficulty in generating high-speed DB-PAM4 signals and the complex adjustment of equalization parameters, this paper proposes a two-step progressive equalization technique. In the first step, the technology transmits not-return-to-zero (NRZ) signals at the transmitter (TX) and generates a Duo-binary (DB) signal path at the receiver using the least mean square error (LMS) algorithm. In the second step, the technology sends a precode-PAM4 (pre-PAM4) signal at TX; at the receiving end, the adaptive equalization algorithm is used to adjust the DSP equalization parameters to generate the optimal equalization parameters of the DB-PAM4 signal. This paper uses Cadence’s AMS simulation platform to verify the receive equalizer of DB-PAM4. Simulation results show: when a 112 Gb/s pre-PAM4 signal passes through the 35 dB@28 GHz channel, the receiver (RX) utilizes the adaptive equalizer to generate a 112 Gb/s DB-PAM4 signal, and the receiver bit error rate (BER) is less than 3e−9.

show abstract

Section: Introductionmentioning

confidence: 99%