Interconnect architecture exploration for low-energy reconfigurable single-chip DSPs

Hui, Zhang; Wan, M.; George, Varghese; Rabaey, Jan M.

doi:10.1109/iwv.1999.760456

Cited by 48 publications

(18 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…A multi-bus network [100] may be used to allow two or three RFUs to simultaneously function for different protocol modes. A segmented bus [100] could also achieve similar results, with lower resources but with some additional control operations involved. All RFUs are fed by the reconfiguration-data-bus and the packet-databus.…”

mentioning

confidence: 77%

See 1 more Smart Citation

A coarse-grained Dynamically Reconfigurable MAC Processor for power-sensitive multi-standard devices

Nabi

Wells

Vanderbauwhede

2008

2008 IEEE International SOC Conference

View full text Add to dashboard Cite

Nabi, Syed Waqar (2009) A coarse-grained dynamically reconfigurable MAC processor for power-sensitive multi-standard devices. EngD thesis.http://theses.gla.ac.uk/865/ Copyright and moral rights for this thesis are retained by the author A copy can be downloaded for personal non-commercial research or study, without prior permission or charge This thesis cannot be reproduced or quoted extensively from without first obtaining permission in writing from the Author The content must not be changed in any way or sold commercially in any format or medium without the formal permission of the Author When referring to this work, full bibliographic details including the author, title, awarding institution and date of the thesis must be given Copyright c Syed Waqar Nabi October 2008In the name of Allah, the Beneficent, the Merciful.Read: In the name of thy Lord Who createth, Createth man from a clot. Read: And thy Lord is the Most Bounteous, Who teacheth by the pen, Teacheth man that which he knew not. Nay, but verily man is rebellious That he thinketh himself independent! Lo! unto thy Lord is the return.The Quran; Chapter 96, Verses 1-7 i Abstract DRMP, a Dynamically Reconfigurable MAC Processor, is an innovative, dynamically reconfigurable System-on-Chip architecture. The architecture exploits substantial overlaps in the functionality of different wireless MAC layers. Its flexibility is specialized for addressing the requirements of the MAC layer of wireless standards. It is targeted at consumer, multi-standard, handheld devices, and its design is meant to address the balance of flexibility and power-efficiency that this target market demands. The DRMP reconfigures packet-by-packet on the fly, allowing execution of concurrent protocol modes on a single hardware co-processor. An interrupt-driven programming model has also been presented and shown to implement the protocol state-machine of the three protocols on a CPU. These features will allow the DRMP to replace three MAC processors in a hand-held device. The most innovative component of the DRMP architecture is its Interface and Reconfiguration Controller. It uses a combination of asynchronous controllers to dynamically reconfigure the functional units in the architecture and delegate MAC tasks to them. The architecture has been modeled in Simulink at cycle-approximate abstraction. Results of simulations involving transmission and reception of packets have been presented, showing that the platform concurrently handles three protocol streams, reconfigures dynamically, yet meets and exceeds the protocol timing constraints, all at a moderate frequency. Its heterogeneous and coarse-grained functional units, limited connectivity requirements between these units, and proportionally large time that these resources are idle, promise a very modest power-consumption, suitable for mobile devices, while offering flexibility to implement different MAC protocols. The Institute of System Level Integration in general, the EngD center and Sian Williams in particular, deserve a special t...

show abstract

mentioning

confidence: 77%

“…E.g. according to [100], a hierarchical interconnect network delivers the best energy efficiency while maintaining flexibility for heterogeneous reconfigurable systems.…”

mentioning

confidence: 99%

A coarse-grained Dynamically Reconfigurable MAC Processor for power-sensitive multi-standard devices

Nabi

Wells

Vanderbauwhede

2008

2008 IEEE International SOC Conference

View full text Add to dashboard Cite

show abstract

“…The PLEIADES project at UC Berkeley [44] proposes an interconnection of a low power FPGA, datapath units, memory, and pro cessors, optimized for different application domains. The PLEIADES researchers conclude that a hierarchical gen eralized mesh interconnect structure [43] is most appro priate for their architecture as it balances both the global and the local interconnect. Our results are in agreement with this conclusion in general but given that we are target ing streaming computations, we have greater emphasis on near-neighbor communication and have stayed away from a general mesh.…”

Section: Related Workmentioning

confidence: 99%

Synchroscalar: a multiple clock domain, power-aware, tile-based embedded processor

Oliver¹,

Rao²,

Sultana³

et al.

Proceedings. 31st Annual International Symposium on Computer Architecture, 2004.

View full text Add to dashboard Cite

show abstract

“…The PLEIADES project at UC Berkeley [21] proposes an interconnection of a low power FPGA, datapath units, memory, and processors, optimized for different application domains. The Pleiades researchers conclude that a hierarchical generalized mesh interconnect structure [22] is most appropriate for their architecture because it balances both the global and the local interconnect. Our results are in agreement with this conclusion in general but given that we are targetting streaming computations such as those encountered in a wirless transceiver, we have greater emphasis on near-neighbor communication, so we have stayed away from a general mesh.…”

Section: Related Workmentioning

confidence: 99%

Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture

Oliver

Rao

Sultana

et al. 2005

Power-Aware Computer Systems

View full text Add to dashboard Cite

Abstract. Embedded devices have hard performance targets and severe power and area constraints that depart significantly from our design in tuitions derived from general-purpose microprocessor design. This paper describes our initial experiences in designing Synchroscalar, a tile-based embedded architecture targeted for multi-rate signal processing applica tions.We present a preliminary design of the Synchroscalar architecture and some design space exploration in the context of important signal process ing kernels. In particular, we find that synchronous design and substan tial global interconnect are desirable in the low-frequency, low-power do main. This global interconnect enables parallelization and reduces pro cessor idle time, which are critical to energy efficient implementations of high bandwidth signal processing. Furthermore, statically-scheduled communication and SIMD computation keep control overheads low and energy efficiency high.

show abstract

Interconnect architecture exploration for low-energy reconfigurable single-chip DSPs

Cited by 48 publications

References 10 publications

A coarse-grained Dynamically Reconfigurable MAC Processor for power-sensitive multi-standard devices

A coarse-grained Dynamically Reconfigurable MAC Processor for power-sensitive multi-standard devices

Synchroscalar: a multiple clock domain, power-aware, tile-based embedded processor

Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture

Contact Info

Product

Resources

About