Interconnect Characterization of X Architecture Diagonal Lines for VLSI Design

Arora, N.D.; Song, Li; Shah, S.; Joshi, Ketan; Thumaty, K.; Fujimura, Aki; Yeh, Long-Ching; Yang, P.

doi:10.1109/tsm.2005.845037

Cited by 13 publications

(5 citation statements)

References 6 publications

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“…As part of copper (Cu) damascene manufacturing process, CMP is also a process employed to keep the planarity of the wafer in order to accommodate today's shrinking lithography process window. However, CMP is a process that heavily depends on the metal width and density and various degrees of dishing and erosion occur at different metal density and line width [3]. To keep thickness uniform, dummy fills are routinely inserted into the layout to obtain uniform density, and hopefully achieve planarity and uniform copper thickness.…”

Section: Cmp Modelingmentioning

confidence: 99%

Integration of CMP Modeling in RC Extraction and Timing Flow

Liao

Song

Jakatdar

et al. 2007

2007 IEEE Custom Integrated Circuits Conference

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As technology scaling progresses into 65nm and below nodes, on chip variation (OCV) specifically interconnect thickness variation due to Chemical Mechanical Polishing (CMP) becomes relatively larger, as such it needs to be taken into consideration in the post layout RC extraction and timing flow. Traditionally manufacturing effects due to lithography and CMP processes are captured using rule based look up tables. These look up tables are included in the technology file of RC extraction tools. However, due to complex nature of CMP process and design topology, the generic rules can not capture thickness variation accurately. Therefore CMP models are used to generate design specific thickness variation profile, based on the calibrated manufacturing process library. In this paper, we demonstrate that by incorporating CMP model in the post layout RC extraction flow, the thickness variations are reflected more accurately and the capacitance value extracted are different from results obtained using the polynomial equation based approach. As a result, new timing violations are detected with CMP modeling.

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Section: Cmp Modelingmentioning

confidence: 99%

Integration of CMP Modeling in RC Extraction and Timing Flow

Liao

Song

Jakatdar

et al. 2007

2007 IEEE Custom Integrated Circuits Conference

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“…Compared to the traditional Manhattan architecture, it can shorten wiring by up to 17% (the maximum reduction of 29% theoretically) across a die [6] in a average case. The utilization of X Architecture is becoming popular, some VLSI chips based on X Architecture have been released (e.g., a GPU chip by ATI in 2005 and a 10Gb Ethernet chip by Teranetics in 2006) according to [2].…”

Section: Architecturementioning

confidence: 99%

Variant X-Tree Clock Distribution Network and Its Performance Evaluations

Zhang¹,

Jiang²,

Horiguchi³

2007

IEICE Transactions on Electronics

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SUMMARY The evolution of VLSI chips towards larger die size, smaller feature size and faster clock speed makes the clock distribution an increasingly important issue. In this paper, we propose a new clock distribution network (CDN), namely Variant X-Tree, based on the idea of X-Architecture proposed recently for efficient wiring within VLSI chips. The Variant X-Tree CDN keeps the nice properties of equal-clock-path and symmetric structure of the typical H-Tree CDN, but results in both a lower maximal clock delay and a lower clock skew than its HTree counterpart, as verified by an extensive simulation study that incorporates simultaneously the effects of process variations and on-chip inductance. We also propose a closed-form statistical models for evaluating the skew and delay of the Variant X-Tree CDN. The comparison between the theoretical results and the simulation results indicates that the proposed statistical models can be used to efficiently and rapidly evaluate the performance of the variant X-Tree CDNs.

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“…As illustrated in Figure 1, the use of diagonal wire to connect two corners results in 29.3% wire length reduction and one via elimination, compared to orthogonal wiring. In practice, based on Monte Carlo simulations, it has been found that on an average there is about 17% wire length reduction for a 90K gates circuit [2]. In a proposed routing example (Figure 1), orthogonal routing is used for most of the lower metal layers, ensuring compatibility with currently used cell libraries.…”

Section: Architecturementioning

confidence: 99%

“…The test chip consists of structures of comb/serpentine, maze, via chain, as well as resistance and capacitance structures that are used to study the electrical properties (resistance and capacitance) of diagonal wires. They were designed using both 90nm and 65nm Cu CMOS processes [2,3]. Comb/serpentine (CS) test structures consist of four quadrants (Figure 2a), all having 2 combs and a serpentine traversing around these combs.…”

Section: Test Structurementioning

confidence: 99%

Investigating a lithography strategy for diagonal routing architecture at sub-100nm technology nodes

Song

Chen²,

Shah

et al. 2005

Design and Process Integration for Microelectronic Manufacturing III

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The X Architecture offers the potential to produce smaller and faster integrated circuits through the pervasive use of 45 wirings on the upper metal layers. The X Initiative members have demonstrated its manufacturability and integrationworthiness at the 130nm, 90nm and 65nm process technology nodes. This paper explores the use of off-axis lithography illumination to print 45 diagonal wires at leading technology nodes. The paper also describes the RET strategies employed for the X Architecture and the effectiveness of various illumination sources at various process nodes. Process window and metal wiring CD variation of Manhattan and X Architecture are compared in the simulations using different types of illuminators. Simulation shows that using 193nm light source, Manhattan and X designs can easily be printed with different types of illuminating source in either 90nm or 65nm process node. Silicon test chips at 90nm that include typical X routing patterns are designed to verify the printability of X Architecture wirings. Electrical measurements as well as SEM analysis are conducted and results show that the fidelity of diagonal wirings is as good as traditional Manhattan routings.

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Interconnect Characterization of X Architecture Diagonal Lines for VLSI Design

Cited by 13 publications

References 6 publications

Integration of CMP Modeling in RC Extraction and Timing Flow

Integration of CMP Modeling in RC Extraction and Timing Flow

Variant X-Tree Clock Distribution Network and Its Performance Evaluations

Investigating a lithography strategy for diagonal routing architecture at sub-100nm technology nodes

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