Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays

Abstract

Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect wires in modern FPGAs now require rebuffering at interior points in the wire. This paper presents a framework for designing and evaluating long, buffered interconnect wires in FPGAs with near-optimal delay performance using HSPICE-derived delays. Given a target physical wire length, width, and spacing, the method determines the number, size, and position of buffers required to obtain the fastest signal velocity for programmable interconnect. While traditional hand-calculations used for ideal repeater placement can be used, they are not very accurate and ignore practical constraints such as the overhead effects of front-end multiplexing and driving logic, Bfinite^wire length, and a discrete number of repeaters. A metric introduced during the design is the Bpath delay profile^, or the arrival time of a signal at different points of a long wire. This method is used to design buffering strategies for interconnect based on 0.5, 2, and 3 mm wire lengths in 180 nm technology. These interconnect designs are coded into VPR along with an improved timing analyzer which accurately determines the Bpath delay profile^arrival times. Using VPR, average critical-path delay is reduced by 19% for 0.5 mm wires and by up to 46% for 3mm wires over previous designs.

Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs

“…The programmable interconnect is assumed to consist of a variable number of identical cascaded stages, each of which includes a 16:1 multiplexer, a driving buffer, and a wire which spans four tiles [18]. Figure 5 shows a circuit schematic of a four-tile wire.…”

“…The multiplexers use full CMOS transmission gates rather than only NMOS transistors to improve risetime, which unfortunately conveys a significant area penalty. The multiplexer design is the hybrid style used in [18] which contains two series transmission gates in the signal path. Throughput tends to be limited by the mux risetime.…”

Automated transistor sizing for FPGA architecture exploration

“…For large multiplexers, the approaches used range from fully encoded multiplexers [3], to two-level partially-decoded structures [8,6]. Similarly, the placement of buffers has also varied between placement at the input to multiplexers (in addition to the output) [1] or simply at the output [8,6]. These implementation choices are left as inputs to allow architects to explore their impact.…”

“…The transistor sizing of buffers for the routing interconnect, similar to that shown in Figure 2, was considered in [6] for 180 nm CMOS. The sizes and test circuit structure used in [6] were simulated 1 and the delay results were compared to those obtained when our optimizer was used.…”

Optimization opportunities in RRAM-based FPGA architectures

“…1(a) and (b) illustrate the schematics of SRAM-based and RRAM-based multiplexers, respectively. We consider a two-level structure for the SRAM-based multiplexers because it guarantees the best area-delay product compared to one-level or multi-level structures [10]. The RRAM-based multiplexer is built with a one-level structure and 4T1R programming elements exploiting I/O transistors [6].…”