Interconnect modeling of global metals for 40nm node

Abingosa, Marion Rey F.; Receno, Clemente; Imperial, John; Hora, Jefferson A.

doi:10.1109/hnicem.2015.7393172

Cited by 6 publications

(3 citation statements)

References 8 publications

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“…Using a wire-load model is the simplest method of estimation. The wire-load model gets a rough value of the total wire capacitance based on the size of the chip and the fanout of the net [26]. The wire-load model is specified in the Liberty file.…”

Section: Power Modelsmentioning

confidence: 99%

A Novel Approach to Design a Process Design Kit Digital for CMOS 180nm Technology

Cong¹,

Le-Thanh²,

Bao³

et al. 2021

Adv. sci. technol. eng. syst. j.

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In this paper, a novel approach to design a Process Design Kit Digital for CMOS 180nm process is presented. This work proposes a detailed flow to design a PDK Digital using Ocean language, which is a vital element in the semi-custom design and applied in education purposes in universities in Vietnam. The PDK digital includes Standard Cell Library containing 47 standard cells and Wire-Load Model. The library is designed based on the CMOS 180nm process with a supply voltage of 1.8V.

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Section: Power Modelsmentioning

confidence: 99%

A Novel Approach to Design a Process Design Kit Digital for CMOS 180nm Technology

Cong¹,

Le-Thanh²,

Bao³

et al. 2021

Adv. sci. technol. eng. syst. j.

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“…This is mainly due to the large capacitance and the high resistance introduced by their extremely small dimensions, which yield considerable signal loss and RC delay [4,5]. For this reason, many attempts to model and characterize BEOL structures and their resistance and capacitance have been recently proposed, including their trend of variation when the geometry is scaled-down [6][7][8][9][10][11][12][13]. Nevertheless, the corresponding properties when operated under AC stimuli have not been studied in detail for deepsub-100 nm technologies [14][15][16].…”

Section: Introductionmentioning

confidence: 99%

Characterizing 10 nm node based BEOL interconnects at low-frequency regime based on a transmission-line modelling approach

Mendez-Jeronimo¹,

Vega-Gonzalez²,

Wilson³

et al. 2018

Semicond. Sci. Technol.

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The signal propagation and impedance features of back-end-of-line interconnects are analysed through the systematic processing of experimental complex impedance data. This is achieved by proposing an equivalent circuit that accounts for the distribution of resistive and capacitive elements on the considered structure. In this regard, due to the relatively long length of the test structures typically used to assess the performance of these interconnects, the corresponding phase delay and attenuation that becomes apparent under AC stimuli need to be considered. Hence, transmission line theory is applied here for maintaining the modelling approach simple but still physical. Accurate results are achieved when correlating simulated with experimental data when using the extracted model parameters.

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“…In addition, these back-end-based RRAMs and MRAMs require large connecting structure, composed of multi-stack of vias and metals to the SRAM cells. These bridging structures increase parasitic capacitance to the SRAM data storage node, affecting the accessing speed of these non-volatile SRAM cells [ 24 , 25 ]. In our previous work [ 26 ], a new zero static power 4T nv-SRAM with STI-sidewall RRAMs located next to the floating storage nodes of 4T SRAM has been firstly proposed.…”

Section: Introductionmentioning

confidence: 99%

A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process

et al. 2017

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This paper reports a novel full logic compatible 4T2R non-volatile static random access memory (nv-SRAM) featuring its self-inhibit data storing mechanism for in low-power/high-speed SRAM application. With compact cell area and full logic compatibility, this new nv-SRAM incorporates two STI-ReRAMs embedded inside the 4T SRAM. Data can be read/write through a cross-couple volatile structure for maintaining fast accessing speed. Data can be non-volatilely stored in new SRAM cell through a unique self-inhibit operation onto the resistive random access memory (RRAM) load, achieving zero static power during data hold.

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Interconnect modeling of global metals for 40nm node

Cited by 6 publications

References 8 publications

A Novel Approach to Design a Process Design Kit Digital for CMOS 180nm Technology

A Novel Approach to Design a Process Design Kit Digital for CMOS 180nm Technology

Characterizing 10 nm node based BEOL interconnects at low-frequency regime based on a transmission-line modelling approach

A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process

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