Interconnection Networks for Scalable Quantum Computers

Isailovic, Nemanja; Patel, Yatish; Whitney, Mark; Kubiatowicz, John

doi:10.1145/1150019.1136505

Cited by 28 publications

(32 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…The third approach was studied in detail in Isailovic et al [2006], where the creation of hundreds of EPR pairs is required between the source and destination to purify EPR pairs that span the entire channel needed. Intuitevely, both the second and third approaches offer much longer final distance than the linear approach employed by the QLA architecture.…”

Section: No Errorsmentioning

confidence: 99%

High-level interconnect model for the quantum logic array architecture

Metodi

Thaker

Cross

et al. 2008

J. Emerg. Technol. Comput. Syst.

View full text Add to dashboard Cite

We summarize the main characteristics of the quantum logic array (QLA) architecture with a careful look at the key issues not described in the original conference publications: primarily, the teleportation-based logical interconnect. The design goal of the the quantum logic array architecture is to illustrate a model for a large-scale quantum architecture that solves the primary challenges of system-level reliability and data distribution over large distances. The QLA's logical interconnect design, which employs the quantum repeater protocol, is in principle capable of supporting the communication requirements for applications as large as the factoring of a 2048-bit number using Shor's quantum factoring algorithm. Our physical-level assumptions and architectural component validations are based on the trapped ion technology for implementing quantum computing.

show abstract

Section: No Errorsmentioning

confidence: 99%

High-level interconnect model for the quantum logic array architecture

Metodi

Thaker

Cross

et al. 2008

J. Emerg. Technol. Comput. Syst.

View full text Add to dashboard Cite

show abstract

“…However, teleportation incurs a substantial hardware cost in the increased number of qubits and number of operations required to purify EPR pairs and requires an extensive networking infrastructure to distribute EPR pairs throughout the chip. Purification has space costs that scale exponentially with the communication distance, and the preparation of each teleportation channel may require hundreds of EPR qubits [11].…”

Section: Quantum Computing Basicsmentioning

confidence: 99%

“…Oskin et al proposed the use of quantum teleportation as a long-range on-chip communication mechanism [20], and it has since become a fundamental component of many QC architecture proposals including ion-trap [17] and solid-state QCs [5]. Isailovic et al detailed and evaluated an interconnection network based on quantum teleportation for ion-trap QCs [11]. They found that EPR pair distribution dominates bandwidth and network design.…”

Section: Related Workmentioning

confidence: 99%

Tailoring quantum architectures to implementation style

Chi

Lyon

Martonosi

2007

Proceedings of the 34th Annual International Symposium on Computer Architecture

View full text Add to dashboard Cite

In recent years, quantum computing (QC) research has moved from the realm of theoretical physics and mathematics into real implementations [9]. With many different potential hardware implementations, quantum computer architecture is a rich field with an opportunity to solve interesting new problems and to revisit old ones. This paper presents a QC architecture tailored to physical implementations with highly mobile and persistent quantum bits (qubits). Implementations with qubit coherency times that are much longer than operation times and qubit transportation times that are orders of magnitude faster than operation times lend greater flexibility to the architecture. This is particularly true in the placement and locality of individual qubits. For concreteness, we assume a physical device model based on electron-spin qubits on liquid helium (eSHe) [15].Like many conventional computer architectures, QCs focus on the efficient exposure of parallelism. We present here a QC microarchitecture that enjoys increasing computational parallelism with size and latency scaling only linearly with the number of operations. Although an efficient and high level of parallelism is admirable, quantum hardware is still expensive and difficult to build, so we demonstrate how the software may be optimized to reduce an application's hardware requirements by 25% with no performance loss. Because the majority of a QC's time and resources are devoted to quantum error correction, we also present noise modeling results that evaluate error correction procedures. These results demonstrate that idle qubits in memory need only be refreshed approximately once every one hundred operation cycles.

show abstract

“…The architectures with this limitation are called nearest‐neighbor architectures. This limitation imposes some communication overhead on the total circuit latency that this communication overhead can also increase error probability .…”

Section: Introductionmentioning

confidence: 99%

Quantum circuit physical design flow for 2D nearest‐neighbor architectures

Farghadan

Mohammadzadeh

2017

Circuit Theory & Apps

View full text Add to dashboard Cite

Summary The physical design process takes a netlist generated by the logic synthesis process and places and routes the netlist on a physical platform. In some physical platforms, physical qubits must be placed on a 2D grid. Each node of the grid represents a qubit. In these platforms, performing quantum gates on non‐adjacent qubits is very error prone or hard to control. Therefore, quantum gates are limited to be performed on adjacent qubits. A communication channel of swap gates needs to be constructed if the qubits in the logical circuit are not adjacent. The algorithms used for mapping of qubits on the grid have important roles in reducing the number of swap gates and thus decreasing of the circuit latency. Focusing on this issue, in this paper, a flow for physical design of quantum circuits on a 2D grid is proposed. It contains three algorithms for finding the order of qubit placement, physical qubit placement, and routing. Simulation results show that the proposed flow not only decreases the average number of swap gates by about 16% compared with the best in the literature but also improves the average runtime by about 94% compared with it. Copyright © 2017 John Wiley & Sons, Ltd.

show abstract

Interconnection Networks for Scalable Quantum Computers

Abstract: We

Cited by 28 publications

References 25 publications

High-level interconnect model for the quantum logic array architecture

High-level interconnect model for the quantum logic array architecture

Tailoring quantum architectures to implementation style

Quantum circuit physical design flow for 2D nearest‐neighbor architectures

Contact Info

Product

Resources

About