Interface Algorithm Design for Power Hardware-in-the-loop Emulation of Modular Multilevel Converter Within High-Voltage Direct Current Systems

Li, Binbin; Xu, Dianguo; Wang, Shengbo; Han, Linjie; Xu, Dianguo

doi:10.1109/tie.2020.3040682

Cited by 10 publications

(4 citation statements)

References 34 publications

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“…DIM is a generalization of ITM and PCD. It has a linking impedance similar to the PCD and includes a damping impedance [8]. DIM is stable as long as the damping impedance matches the impedance of PDuT.…”

Section: Introductionmentioning

confidence: 99%

New Power Interface Based on Multi-Dimensional Golden Section Search Algorithm for Power-Hardware-in-the-Loop Applications

Constantine,

Lian,

Fan

et al. 2024

IEEE Access

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Power-Hardware-in-the-Loop (PHIL) is a kind of real-time simulation, capable of exchanging not just low-voltage, low current signals, but the power required by the power device under test (PDuT). PHIL requires a PDuT to be connected to a real-time digital power network simulator via a power interface (PI). There have been quite a few PIs proposed in the past. Among them, ideal transformer model (ITM) is the most commonly used due to its ease of implementation. Other PIs such as partial circuit duplication and damping impedance can be considered as an extended version of ITM. These PIs need to follow a strict impedance ratio between PDuT and the rest of the system prior to the PHIL implementation, which could be a tedious and difficult task. This paper proposed a new PI for PHIL based on multi-dimensional golden section search algorithm, which can eliminate such a constraint. The proposed method has been shown to have wider stability regions when PDuT is a passive device or active one such as an inverter based resource. Moreover, dynamic responses of the proposed method are similar to those of the ITM under stable conditions. The validity of the proposed method has been justified with offline simulation and experimental PHIL setups.INDEX TERMS Real-Time Simulation, Power Hardware-in-the-Loop (PHIL), Golden Section Search (GSS), Gauss-Seidel, Power Amplifier.

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Section: Introductionmentioning

confidence: 99%

New Power Interface Based on Multi-Dimensional Golden Section Search Algorithm for Power-Hardware-in-the-Loop Applications

Constantine,

Lian,

Fan

et al. 2024

IEEE Access

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“…Also, the capital expenditure to own power amplifiers capable of driving high power DUTs is significantly higher. Due to these practical limitations, scaled-down converters (SDCs) are commonly used as DUTs to emulate real full-size converters (FSCs) [6]- [8]. However, an accurate scaling and interface methodology is essential for a realistic PHIL simulation, especially when the physical system is a reduced scale DUT and the concerned study focuses on FSC harmonic injection or absorption.…”

Section: Introductionmentioning

confidence: 99%

“…The test aims to study the behavior of the PMSG for frequency regulation support and the entire wind farm is modeled as a controllable current source passed through a low-pass filter (100 Hz cutoff) leaving behind the harmonics. In [6], a scaled-down 3 kW modular multilevel converter (MMC) is employed to emulate a 1500 MW full-scale MMC using average models neglecting the switching harmonics. Type 3 and 4 [15] wind turbines of 2 MW and 600 kW, respectively, are emulated with 75 kVA voltage source converters by [8] who perform the scaling up to the emulated high-power system through a controlled power source while mentioning the advantage of using similar L filters both in the simulated and physical systems but do not discuss the impedance mismatch of the L filter.…”

Section: Introductionmentioning

confidence: 99%

Harmonic-Invariant Scaling Method for Power Electronic Converters in Power Hardware-in-the-Loop Test Beds

Mota

Banda

Adeyemo

et al. 2023

IEEE Open J. Ind. Applicat.

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Power hardware-in-the-loop (PHIL) is an experimental technique that uses power amplifiers and real-time simulators for studying the dynamics of power electronic converters and electrical grids. PHIL tests provide the means for functional validation of advanced control algorithms without the burden of building high-power prototypes during early technology readiness levels. However, replicating the behavior of high-power systems with laboratory scaled-down converters (SDCs) can be complex. Inaccurate scaling of the SDCs coupled with an exclusive focus on instantaneous voltages and currents at the fundamental frequency can lead to PHIL results that are only partially relatable to the high-power systems under study. Test beds that fail to represent switching frequency harmonics cannot be used for studying harmonic penetration or loss characterization of large-scale converters. To tackle this issue, this paper proposes a harmonic-invariant scaling method (HISM) that exploits the VA rating of preexisting laboratory SDCs for more accurately replicating harmonic phenomena in a PHIL test bench. Firstly, a theoretical analysis of the proposed method is presented and, subsequently, the method is validated with MATLAB simulations and experimental tests.INDEX TERMS Hardware-in-the-loop, Power conversion harmonics, Real-time emulation, Voltage source converter, Large-scale systems.

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“…P OWER hardware-in-the-loop (PHIL) plays a significant role in accelerating the research and development of power technologies by enabling repeated and non-destructive real-time testing under a broad range of scenarios [1]- [10]. This advanced real-time testing methodology has been extensively leveraged for the in-depth modelling and assessment of renewable energy technologies including photovoltaic system [3], [4], energy storage system [5], variable-speed wind turbines [6], etc., prototyping of power apparatus [2], [7], verification of control strategies [8], black start testing of gridforming converter [9], and power system education [10].…”

mentioning

confidence: 99%

Adaptive Smith Predictor for Enhanced Stability of Power Hardware-in-the-Loop Setups

Feng

Peña-Alzola

Syed

et al. 2023

IEEE Trans. Ind. Electron.

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The stability and accuracy of power hardware-inthe-loop (PHIL) setups are sensitive to and deteriorated by the dynamics and non-ideal characteristics of their power interfaces, such as time delay, noise perturbation, and signal distortion. In this paper, a compensation scheme comprising a Smith predictor compensator is proposed to mitigate the impact of time delay on PHIL stability. Furthermore, an online system impedance identification technique is leveraged to enhance the robustness of the compensator and facilitate the compensation scheme with adaptivity to system impedance variation. Analytical assessment, simulation results, and PHIL experimental results are presented to verify the proposed compensation scheme. This scheme enables robust and stable testing of novel power technologies under varying impedance ratios representative of the complex scenarios emerging within the power sector.

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Interface Algorithm Design for Power Hardware-in-the-loop Emulation of Modular Multilevel Converter Within High-Voltage Direct Current Systems

Cited by 10 publications

References 34 publications

New Power Interface Based on Multi-Dimensional Golden Section Search Algorithm for Power-Hardware-in-the-Loop Applications

New Power Interface Based on Multi-Dimensional Golden Section Search Algorithm for Power-Hardware-in-the-Loop Applications

Harmonic-Invariant Scaling Method for Power Electronic Converters in Power Hardware-in-the-Loop Test Beds

Adaptive Smith Predictor for Enhanced Stability of Power Hardware-in-the-Loop Setups

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