Interface control and electron transport in ALD ZnO/Al₂O₃ TFTs studied by gated Hall effect

Abstract

Many challenges exist in understanding transport properties in metal-oxide thin film transistors (MO-TFTs). Microstructural disorder, dielectric/active layer interface trap states, and grain boundaries contribute to reductions in device properties such as transistor output current, mobility, and sheet carrier concentration. In this work, we use scheduled interruptions during atomic layer deposition combined with a series of thermal anneals to control properties of ZnO/ A l 2 O 3 TFTs, and to experimentally decouple physical effects within the TFT affecting device performance. Using concurrent current–voltage and gated Hall effect measurements, we observe two sets of trends for these devices. In the first, increasing post-temperature anneal is shown to improve the device characteristics by reducing grain boundary effects. In the second, exposure to ambient conditions is shown to increase the number of interface trap states. Comparisons of measured values show that these trap states enhance some properties of the lower temperature annealed series, while degrading these values in the higher temperature annealed series. We show that this is due to devices acting in two separate transport regimes: localized, and non-localized. We investigate the position of the Fermi level, adjusted by gate bias, to these two regimes under each test condition, and suggest a simple model to describe the results.