Interface optimization during hardware-software partitioning

Freund, L.; Dupont, D.; Israel, M.; Rousseau, Frédéric

doi:10.1109/hsc.1997.584582

Cited by 8 publications

(3 citation statements)

References 9 publications

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“…Since delays due to data transfers between HW and SW units are very dependent on this data distribution, effects of communications on produced solutions should also be considered during partitioning of the specification in order to exhibit HW/SW systems that respect firmly cost and timing constraints [Freund et al 1997]. In addition, some computationally intensive applications require transfers of arrays between processing units that may be pipelined or overlapped with computations of nodes.…”

Section: Discussionmentioning

confidence: 99%

A codesign experiment in acoustic echo cancellation

Freund

Israel

Rousseau³

et al. 1997

ACM Trans. Des. Autom. Electron. Syst.

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International audienceContinuous advances in processor and ASIC technologies enable the integration of more and more complex embedded systems. Embedded systems have become commonplace in recent years. Since their implementations generally require the use of heterogeneous resources (e.g., processor cores, ASICs) in one system with hard design constraints, the importance of hardware/software codesign methodologies increases steadily. HW/SW codesign approaches consist generally of HW/SW partitioning and scheduling, constrained code generation, and hardware and interface synthesis. This article presents the codesign of an industrial experiment in acoustic echo cancellation (GMDF&agr; algorithm); and emphasizes the partitioning and communication synthesis steps. This experiment brings to light interesting problems such as data and program distribution between system memories and the modeling of communications in the partitioning proces

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Section: Discussionmentioning

confidence: 99%

A codesign experiment in acoustic echo cancellation

Freund

Israel

Rousseau³

et al. 1997

ACM Trans. Des. Autom. Electron. Syst.

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“…Some techniques of partitioning and scheduling represent system in form of Directed acyclic graph (DAG) [4] .The main limitation with these methodology is that not only the size of DAG, that is system specific, increase but other constraints like communication nodes added for interface makes DAG significantly large and makes computation more complex. There are layout-conscious approaches also for hardware/software codesign for systems-on-chip (SoCs) that are optimized for latency [5].…”

Section: Introductionmentioning

confidence: 99%

A combinatorial digital circuit with evolutionary algorithm for evolvable hardware software codesign

Srivastava

2010

2010 International Conference on Power, Control and Embedded Systems

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The theory of evolution is equally well applied on the electronic digital circuit configuration. The genetic algorithm (GA) is an optimization and search technique based on the principles of genetics and natural selection. Genetic algorithm one of the classifications of evolutionary algorithm, is an upcoming area for the designing of reprogrammable hardware. The fitness function decides whether to accept new chromosome for the next generation or not. These functions incorporate various factors that evolve a constrained and much optimized hardware. Our aim in this paper is to present a simple method to synthesize a combinatorial digital circuit with some fitness functions required for any VLSI circuit and reduce the gate complexity of the circuit.

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“…These approaches enable the accurate evaluation of system architecture performance, but the development term of complex bus architecture modeling and the simulation performance of large system are critical issues. Others are based on the synthesis algorithm of bus communication architecture ( [7], [8], [9]). However, we have recently seen a dramatic increase in the range of possible hardware bus architecture configurations, and their influence on optimum performance with a certain class of application.…”

Section: Introductionmentioning

confidence: 99%

A practical approach for bus architecture optimization at transaction level

Ogawa¹,

Noyer²,

Chauvet³

et al.

2003 Design, Automation and Test in Europe Conference and Exhibition

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For multimedia applications, the System LSI design trend is to integrate an increasing number of applications running on a single chip. Traditional architectures have reached their limit in terms of performance. New architectures must be explored to fulfill the system application needs. Complex bus structures have been introduced. These bus architectures open a much larger exploration space than traditional hardware-software partitioning trade-offs. We have been researching methods to leverage these new architectural elements. We also introduce a design environment to apply practical and efficient methods in today's design flow. Two key technologies are supporting our method and environment: Automatic bus architecture synthesis for easy configuration of bus architecture and transaction level of abstraction for communication for improvement of simulation performance. In this paper, we show the design method, an overview of the design environment and its usefulness through experimental results.

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Interface optimization during hardware-software partitioning

Cited by 8 publications

References 9 publications

A codesign experiment in acoustic echo cancellation

A codesign experiment in acoustic echo cancellation

A combinatorial digital circuit with evolutionary algorithm for evolvable hardware software codesign

A practical approach for bus architecture optimization at transaction level

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