Interface Optimization of Passivated Er2O3/Al2O3/InP MOS Capacitors and Modulation of Leakage Current Conduction Mechanism

Qiao, Lesheng; He, Gang; Hao, Lin; Lü, Jinyu; Gao, Qian; Zhang, Miao; Fang, Zebo

doi:10.1109/ted.2021.3072928

Cited by 14 publications

(12 citation statements)

References 29 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The apparent shift of the conductivity peak proves the validity of the Fermi-level shift and confirms the existence of the Fermi-level deconvolution effect [38]. Assuming that the underlying surface oscillations can be neglected, the value of D it is inferred using the normalized parallel conductivity peak (G P /ω) max [39].…”

Section: Conductivity-voltage Measurementssupporting

confidence: 64%

Interface Optimization and Transport Modulation of Sm2O3/InP Metal Oxide Semiconductor Capacitors with Atomic Layer Deposition-Derived Laminated Interlayer

Lü

Yan

et al. 2021

Nanomaterials

Self Cite

View full text Add to dashboard Cite

In this paper, the effect of atomic layer deposition-derived laminated interlayer on the interface chemistry and transport characteristics of sputtering-deposited Sm2O3/InP gate stacks have been investigated systematically. Based on X-ray photoelectron spectroscopy (XPS) measurements, it can be noted that ALD-derived Al2O3 interface passivation layer significantly prevents the appearance of substrate diffusion oxides and substantially optimizes gate dielectric performance. The leakage current experimental results confirm that the Sm2O3/Al2O3/InP stacked gate dielectric structure exhibits a lower leakage current density than the other samples, reaching a value of 2.87 × 10−6 A/cm2. In addition, conductivity analysis shows that high-quality metal oxide semiconductor capacitors based on Sm2O3/Al2O3/InP gate stacks have the lowest interfacial density of states (Dit) value of 1.05 × 1013 cm−2 eV−1. The conduction mechanisms of the InP-based MOS capacitors at low temperatures are not yet known, and to further explore the electron transport in InP-based MOS capacitors with different stacked gate dielectric structures, we placed samples for leakage current measurements at low varying temperatures (77–227 K). Based on the measurement results, Sm2O3/Al2O3/InP stacked gate dielectric is a promising candidate for InP-based metal oxide semiconductor field-effect-transistor devices (MOSFET) in the future.

show abstract

Section: Conductivity-voltage Measurementssupporting

confidence: 64%

Interface Optimization and Transport Modulation of Sm2O3/InP Metal Oxide Semiconductor Capacitors with Atomic Layer Deposition-Derived Laminated Interlayer

Lü

Yan

et al. 2021

Nanomaterials

Self Cite

View full text Add to dashboard Cite

show abstract

“…Along with the increase of interfacial stability, the content of In(PO 3 ) 3 shows a decrease to produce the more stable compound InPO 4 . The process is illustrated by the following reaction equation 8 In + 4 In false( PO 3 false) 3 → 3 InP + 9 InPO 4 …”

Section: Resultsmentioning

confidence: 99%

“…18,25 In a previous report, erbium oxide (Er 2 O 3 ) as a gate dielectric could produce a good stoichiometric interface with InP and obtain MOS devices with outstanding performance. 26 When ErSmO films are prepared as gate dielectrics, this high-k system can possess better interfacial quality and fewer defects. Furthermore, it is imperative to use a new means of interfacial passivation to remove the native oxides from the substrate surface and to improve the deposition-induced degradation.…”

Section: Introductionmentioning

confidence: 99%

“…Current advances in depositing high-k gate dielectrics on III–V semiconductors offer the possibility of fabricating high-performance MOS devices that can effectively address interface quality issues. , Among high-k dielectric materials, samarium oxide (Sm 2 O 3 ) has been used as a gate dielectric for InP-based MOS capacitors . Samarium oxide is considered an ideal gate dielectric that can replace silicon dioxide in the future because of its high dielectric constant (∼15), large band gap (5.1 eV), large conduction band shift, low hygroscopicity, and good thermal stability. − However, the deposition of Sm 2 O 3 dielectrics on InP substrates shows apparent frequency dispersion and a large interface density state, which may arise from the mismatch between the fractional charge of InP and the integer charge of Sm 2 O 3 , along with the unstable interface problem formed by the interdiffusion of the dielectric and InP interfaces. , In a previous report, erbium oxide (Er 2 O 3 ) as a gate dielectric could produce a good stoichiometric interface with InP and obtain MOS devices with outstanding performance . When ErSmO films are prepared as gate dielectrics, this high-k system can possess better interfacial quality and fewer defects.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Interface Chemistry and Defect State Optimization of the ErSmO/InP Heterojunction Modified by ALD-Driven Al₂O₃ Interlayers

Lü

Wang

et al. 2023

ACS Appl. Electron. Mater.

Self Cite

View full text Add to dashboard Cite

In this work, the effects of the atomic-layer deposition (ALD)-derived Al2O3 passivation layer with different growth cycles on the interfacial chemistry and electrical performance of sputtering-driven ErSmO/InP metal oxide semiconductor (MOS) capacitors have been comparatively investigated. Atomic force microscopy (AFM) and X-ray photoelectron spectroscopy (XPS) characterization have confirmed that the ALD-driven Al2O3 passivation layer with 20 growth cycles could form a flat dielectric layer and effectively suppress the diffusion of In and P elements at the InP interface. Meanwhile, the ErSmO/Al2O3/InP gate stack with 20 growth cycles exhibited optimal electrical properties, including a large dielectric constant of 37.42, a minimum interface state density (D it) of 5.43 × 1011 eV–1 cm–2, and a low leakage current of 3.95 × 10–6 A/cm–2. The leakage current conduction mechanisms of InP-MOS capacitors measured at room temperature and low temperature have also been systematically analyzed. Particularly, low-frequency noise (LFN) is used to evaluate trap levels in InP-MOS capacitors. All experimental results have demonstrated that the ErSmO/Al2O3/InP gate stack has potential applications in future ultrahigh-speed and high-frequency microelectronic devices.

show abstract

“…Here, we focus on the top gate insulators, excluding the recently reported back gate insulators using high-κ dielectrics (EOT<1 nm) such as perovskite strontium titanium oxide [36] and calcium fluoride. [37] Typical κ values of oxide films on a Si substrate including HfO 2 , [38][39][40] ZrO 2 , [38,41,42] Er 2 O 3 , [26,43,44] Y 2 O 3 , [45][46][47] Al 2 O 3 , [48][49][50] h-BN, [51] and PTCDA [16] are represented as lines on the right in the figure. It is evident that the κ of the ALD oxide that was deposited directly on monolayer MoS 2 was often lower than that on the Si substrate.…”

Section: Demonstration Of the Top-gated Mos 2 Fet With A High-k Insul...mentioning

confidence: 99%

A Monolayer MoS₂ FET with an EOT of 1.1 nm Achieved by the Direct Formation of a High‐κ Er₂O₃ Insulator Through Thermal Evaporation

Uchiyama

Maruyama

Chen

et al. 2023

Small

View full text Add to dashboard Cite

semiconductors, including Si and Ge, the mobility drastically degrades when the channel thickness of the conductor is below 5 nm due to thickness-fluctuationinduced scattering. [2] On the other hand, 2D materials maintain high mobility even under the monolayer limit (0.3-0.6 nm) [3][4][5] and exhibit inherently high on-current, as evidenced by the stronger quantummechanical effect that is observed. [6] In particular, transition metal dichalcogenides (TMDCs) are attractive materials for semiconductor channels of nanoscale FETs because of their high stability against oxidation [7] as well as their superior electrical properties, such as a large bandgap and relatively high carrier mobility. [3][4][5] Here, the large challenge with 2D-FET always involves the formation of highquality ultrathin high-κ oxide insulators. The atomic layer deposition (ALD) of dielectrics on TMDCs has a disadvantage in that high capacitive top gate stacks are formed on TMDCs because the nucleation of the oxide predominantly occurs at defect sites or through the physical adsorption of precursors onto the surface due to the absence of dangling bonds, [8] as shown in Figure 1a. Therefore, thick dielectrics are required to cover the whole surface without pinholes. [9] To form thin oxides with high dielectric constants by the ALD method, it is necessary to intentionally form nucleation sites on TMDCs. In fact, various surface modification methods, including surface treatment [10,11] and the formation of a buffer layer, [12][13][14][15][16][17][18] have been reported for oxide formation on TMDCs with high uniformity and dielectric properties. A surface treatment, including O 2 plasma [10] and ultraviolet ozone, [11] has improved the coverage and uniformity of ALD oxide on TMDCs; however, this treatment induces additional defects that produce extra scattering sites or dopants on TMDCs.The deposition of a buffer layer, including thin metal layers [12][13][14][15] and organic molecules, [16][17][18] is an effective method to provide nucleation sites without forming defects. To date, the thinnest equivalent oxide thickness (EOT) of 1 nm on monolayer TMDCs has been successfully reported by combining an organic monolayer of 3,4,9,10-perylene-tetracarboxylic dianhydride (PTCDA) and ALD-HfO 2 for the top gate stack. [18] However, due to the quite low dielectric constant of PTCDA

show abstract

Interface Optimization of Passivated Er₂O₃/Al₂O₃/InP MOS Capacitors and Modulation of Leakage Current Conduction Mechanism

Cited by 14 publications

References 29 publications

Interface Optimization and Transport Modulation of Sm2O3/InP Metal Oxide Semiconductor Capacitors with Atomic Layer Deposition-Derived Laminated Interlayer

Interface Optimization and Transport Modulation of Sm2O3/InP Metal Oxide Semiconductor Capacitors with Atomic Layer Deposition-Derived Laminated Interlayer

Interface Chemistry and Defect State Optimization of the ErSmO/InP Heterojunction Modified by ALD-Driven Al₂O₃ Interlayers

A Monolayer MoS₂ FET with an EOT of 1.1 nm Achieved by the Direct Formation of a High‐κ Er₂O₃ Insulator Through Thermal Evaporation

Contact Info

Product

Resources

About

Interface Optimization of Passivated Er2O3/Al2O3/InP MOS Capacitors and Modulation of Leakage Current Conduction Mechanism

Cited by 14 publications

References 29 publications

Interface Optimization and Transport Modulation of Sm2O3/InP Metal Oxide Semiconductor Capacitors with Atomic Layer Deposition-Derived Laminated Interlayer

Interface Optimization and Transport Modulation of Sm2O3/InP Metal Oxide Semiconductor Capacitors with Atomic Layer Deposition-Derived Laminated Interlayer

Interface Chemistry and Defect State Optimization of the ErSmO/InP Heterojunction Modified by ALD-Driven Al2O3 Interlayers

A Monolayer MoS2 FET with an EOT of 1.1 nm Achieved by the Direct Formation of a High‐κ Er2O3 Insulator Through Thermal Evaporation

Contact Info

Product

Resources

About

Interface Optimization of Passivated Er₂O₃/Al₂O₃/InP MOS Capacitors and Modulation of Leakage Current Conduction Mechanism

Interface Chemistry and Defect State Optimization of the ErSmO/InP Heterojunction Modified by ALD-Driven Al₂O₃ Interlayers

A Monolayer MoS₂ FET with an EOT of 1.1 nm Achieved by the Direct Formation of a High‐κ Er₂O₃ Insulator Through Thermal Evaporation