Interfacial Layer Engineering Using Thulium Silicate/Germanate for High-k/Metal Gate MOSFETs

Abstract

Thulium silicate (TmSiO) is considered as high-k interfacial layer in high-k/metal gate stacks, providing advantages in terms of EOT scalability and enhanced inversion layer mobility. In this work, we show that optimized annealing conditions for the TmSiO/HfO 2 /TiN gate stack provide competitive gate leakage current density, symmetric nFET and pFET threshold voltages, while retaining compatibility with CMOS processing and ~20% higher electron and hole mobility than literature data on optimized SiO x /HfO 2 stacks at EOT as low as 0.65 nm. We also evaluate cleaning procedures to facilitate thulium germanate formation on Ge channel materials and found that HF cleaning optimization is needed to allow thulium germanate formation while keeping surface roughness at an acceptable level.

(Invited) TmSiO as a CMOS-Compatible High-k Dielectric

“…TmSiO/HfO2/TiN MOSFETs were fabricated using a simplified gate-last CMOS flow for long-channel devices (LG = 3 µm), aimed at evaluating the gate stack performance without influence of short-channel effects (36). Optimized annealing conditions for the gate stack were implemented, involving a post-deposition anneal (PDA) in dilute O3 ambient at 350 °C and forming gas anneal (FGA) in 10% H2/N2 at 400 °C (37). Uniform and reproducible IDVG characteristics were measured for nFETs and pFETs, achieving EOT as low as 0.6 nm, subthreshold slopes ~70 mV/dec, gate current density comparable to scaled SiOx/HfO2 nFETs (~0.7 A/cm 2 at 1 V gate voltage and EOT = 0.8 nm, Fig.…”