Interfacial reliability and micropartial stress analysis between TSV and CPB through NIT and MSA

Abstract

As Moore predicted in 1965, the scale of microelectronic devices continues to diminish at tremendous speed, and today the limitations of conventional 2D scaling make such 3D applications as TSV (through-silicon via) and high-stacked thin-die packaging technologies extremely attractive. However, their complicated structures and thermal-cycled processes generate enormous interfacial stresses. In particular, TSV-to-CPB (copper pillar bump)-stacked structures manufactured under various processing conditions have serious stress-induced reliability problems: stresses can be high enough to cause delaminated or open-crack failures. Many technologies have been developed for measuring residual stress, but destructive techniques such as the holedrilling and cutting methods are too bulky to use at microscales and non-destructive techniques such as XRD (Xray diffraction), BN (Barkhausen noise) and the curvature method using the Stoney equation yield averaged results that are inappropriate in the local assessment of TSV and CPB interfaces. NIT (nanoinstrumented indentation testing), on the other hand, offers many advantages since it can give a micropartial characterization of stress using the load difference between samples with different residual stresses at the same depth. Here we introduce an algorithm to measure the micropartial residual stress between CPB and TSV through nanoinstrumented indentation testing. To verify our measured outputs, we observe cross-sectioned microstructure of TSV and CPB using an ion miller and ion-beam image by FIB (focused ion beam), and discuss the textures of variously structured and processed TSV and CPB interfaces. In addition, we used finite element analysis (ABSYS) to simulate the stress distribution around them. Our study will, we hope, be useful in reliability-based quantitative design by defining keep-out zones between TSVs.Keywords: TSV (through silicon via); Micropartial residual stress; NIT (nanoinstrumented indentation testing); Grain growth model; 3DI (3-dimensional integration). IntroductionAs conventional 2D scaling of microelectronic devices has severe limitations, 3D chip stacking is clearly attractive for high performance at low cost in applications such as CMOS image sensors (CIS), stacked memories, highperformance processor-memory assemblies and advanced system-in-package (SiP) leading to heterogeneous integration.

Online Fault Tolerance Technique for TSV-Based 3-D-IC

“…Lee et al [5] show that thermal stress can damage TSV interconnects, leading to delamination at TSV interface with the bonding pad. Void growth can also occur during normal operation due to thermal load [6].…”

“…These challenges are highlighted and novel solutions have been proposed for improving testability [7]- [10], yield, and reliability [11]- [16]. Various types of TSV defects caused by manufacturing process and thermal stress are highlighted in [4] and [5]. Out of all these defects, this brief focuses on three TSV defects: 1) void; 2) delamination between TSV and landing pad; and 3) TSV short-to-substrate, as these have been extensively studied by test community as highlighted by [7]- [10].…”

Microstructure and stress characterization around TSV using in-situ PIT-in-SEM

“…The via-middle scheme is proper for enhancing poor design flexibility in the via-last process and overcomes both compatibility problems with conventional packaging processes and the high-resistivity difficulty of poly-silicon to meet the temperature conditions of FEOL (front end of line) above 1000℃ in the via-first process. Moreover, copper is the best material for via-filling because it can fill a comparatively large volume and has good electrical performance [1][2]. Nevertheless, copper-filled TSVs experience many reliability problems due to the many thermal loading processes such as BEOL (back end of line), wafer-level bumping, and packaging processes over 350-400℃ after the via-middle process.…”

“…Finally, the most serious copper-induced issue is the thermal stresses that can be large enough to cause TSV-pumping (or extrusion) between the copper TSV and the silicon wafer, ductile fracture at the bump interfaces, UBM (under-bump metal) and device metallization, and electric degradation due to the change in carrier mobility [2][3]. The stress-induced failure modes and mechanisms can be classified into three groups according to the origin of stress [2]. The Cu area (inside the TSV) has two stress-generating mechanisms: extrinsic thermal stress due to CTE mismatch and intrinsic stress due to rapid grain growth during the thermally loaded processes.…”

“…In addition, the positively ionized copper, which has comparatively easy reduction characteristics, migrates easily and is deposited as dendrites at the cathode or as CAF (conductive anodic filaments) at the anode after the preconditioning reliability test such as THB (temperaturehumidity biased) or HAST (highly accelerated biased temperature and humidity stress test); which cause the electrical short or the leakage failure. Finally, the most serious copper-induced issue is the thermal stresses that can be large enough to cause TSV-pumping (or extrusion) between the copper TSV and the silicon wafer, ductile fracture at the bump interfaces, UBM (under-bump metal) and device metallization, and electric degradation due to the change in carrier mobility [2][3]. The stress-induced failure modes and mechanisms can be classified into three groups according to the origin of stress [2].…”