Interposer design and measurement with various caparcitors for reducing total system PDN impedance

Abstract

CMOS digital VLSIs require lower power supply impedance to maintain stable logic operation. This paper reports PDN design and characterization of interposers with different types of decoupling capacitors and different locations. The developed interposer which consisted of six conductive layers was attached on a mother board. Three kinds of locations of decoupling capacitors were examined to reduce power supply impedance. They were die-side capacitors, embedded capacitors, and land-side capacitors on the interposer. Then, three types of capacitors; conventional two-terminal capacitor, L/W reversed type capacitor, and three-terminal capacitor were compared. The CMOS test chip was assumed to synthesize total PDN impedance seen from the chip. By adopting chip-package-board co-design methodology, anti-resonance peaks in total PDN which occured by the interaction between package inductance and on-die capacitance were estimated by simulation.