Interval-based models for run-time DVFS orchestration in superscalar processors

Abstract

We develop two simple interval-based models for dynamic superscalar processors. These models allow us to: i) predict with great accuracy performance and power consumption under various frequency and voltage combinations and ii) implement targeted DVFS policies at run-time. The models analyze program execution in intervals -steady-state and miss-event intervals. Intervals are signalled by miss events (L2-misses in our case) that upset the "steady state" execution of the program and are ended when the pipeline reaches again a steady state. The first model is fed by an approximation of the stall cycles (the time the processor instruction window is blocked) due to long-latency L2-misses. The second model improves on this approximation using as input the occupancy of the L2's miss-handling registers (MSHRs). Despite their simplicity these models prove to be accurate in predicting the performance (and energy) for any target frequency/voltage setting, yielding average errors of 2.1% and 0.2% respectively. Besides modelling, we show that the methodology we propose is powerful enough to implement (at run-time) various DVFS policies: "operate at optimal EDP" or "ED 2 P," or even "reduce ED 2 P within specific performance constraints." Approaches based on the two models require minimal hardware cost: two counters for measuring the duration of the steady state and the miss-event intervals and some comparison logic. To validate our methodology we use a cycle-accurate simulator and the benchmarks provided by the SPEC2K suite. Our results indicate that our proposed run-time mechanism is able to orchestrate different DVFS policies with great success yielding negligible errors -bellow 1.5% on average.

Inter-Cluster Thread-to-Core Mapping and DVFS on Heterogeneous Multi-Cores

“…L1 in Odroid-XU3), the number of instructions executed and MRPI could be low. However, the penalty (measured in cycles) will remain intact no matter what the frequency is, because a branch miss-prediction involves only in-core operations [37]. Therefore, the workload will be treated as compute-intensive and the highest frequency is selected to minimize performance loss.…”

Embedded reconfigurable computing: the ERA approach

“…Figure 5 depicts a high-level view of the proposed reconfiguration framework. The idea behind our approach is that there is a great synergy between the following system parameters: i) Voltage/frequency level of the core (using core DVFS [8]), and ii) processor instruction window (leveraging dynamic core issue-width resizing), and iii) effective LLC size (controlled by cache resizing techniques [9]). As shown in Fig.…”

“…Finally, the bottom-line idea in our framework is that an orthogonal parameter in this reconfiguration triangle is the notion of memory-level parallelism (MLP) in LLC misses (case 6). The importance of MLP is highlighted in a separate publication [8].…”

Predicting Performance Impact of DVFS for Realistic Memory Systems

“…Leading Loads. Leading loads [12,20,34] is a state-of-theart DVFS performance predictor for out-of-order processors. The leading loads predictor was designed based on two simplifying assumptions about the memory system: 1. all memory requests have the same latency, and 2. after an instruction fetch or a data load misses in the last level cache and generates a memory request, the processor continues to execute but eventually runs out of ready instructions and stalls before the memory request returns.…”

“…Recently, two DVFS performance predictors have been proposed: leading loads [12,20,34] 1 and stall time [12,20]. Both assume a linear DVFS performance model, which, as we show in Section 3.2, does not model the performance effects of prefetching.…”