Intra- and inter-processor hybrid performance modeling for MPSoC architectures

Ophelders, Frank; Chakraborty, Samarjit; Corporaal, Henk

doi:10.1145/1450135.1450156

Cited by 6 publications

(3 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In [11], [12] a hybrid approach is taken that combines realtime calculus with simulation in order to produce trace based timing values. The approach in [11], [12] requires the formal modelling of chosen application tasks, thus requiring much time and effort. In [13] the abstraction of specific application tasks is avoided by abstracting their platform's Real-Time Operating System (RTOS).…”

Section: Related Workmentioning

confidence: 99%

Conservative application-level performance analysis through simulation of MPSoCs

Nelson

Hansson

Corporaal

et al. 2010

2010 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia

Self Cite

View full text Add to dashboard Cite

Abstract-Applications, often with real-time requirements, are mapped onto Multiprocessor Systems on Chip (MPSoCs). Hard real-time applications require no deadline misses, and a formal modelling approach must be used to analyse the worst-case performance, which is complicated and time consuming. Such models are restricted to specific application behaviours and not generally applicable. Soft real-time applications such as video decoders often do not fit these models while having less strict requirements. An infrequent frame drop is barely noticeable, and a worst-case analysis is too pessimistic. For such applications it suffices to meet deadlines for a given set of traces.In this work we propose conservative simulation as an alternative approach to formal modelling for soft real-time applications. We introduce a hybrid simulation method which enables performance guarantees on a per-trace basis, without any modelling effort. Furthermore we evaluate an implementation of the described technique and compare it with an actual MPSoC instance implemented on an FPGA. Our results show that the simulation technique is conservative, with less than a 10% difference in timing compared to the actual implementation, for a software JPEG decoder.

show abstract

Section: Related Workmentioning

confidence: 99%

Conservative application-level performance analysis through simulation of MPSoCs

Nelson

Hansson

Corporaal

et al. 2010

2010 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia

Self Cite

View full text Add to dashboard Cite

show abstract

“…Abstraction levels are combined sequentially in time. In [25], the authors combine two system descriptions in order to model and simulate a specific component (written in SystemC) in a system described and analyzed with Real-Time Calculus. Here, the combination of different abstraction levels is done at a spatial level, each component being described in one of the formalisms.…”

Section: Related Workmentioning

confidence: 99%

Evaluation of the implementation cost of cache coherence protocols using omniscient actions

Massas

Pétrot

2010

Des Autom Embed Syst

View full text Add to dashboard Cite

International audienceThis paper presents a novel simulation-based approach which targets the performance estimation of cache coherence protocol implementations. Our approach allows to model a cache coherence protocol where coherence transactions take zero cycle and do not generate communication accesses, in the hope that it will provide a close lower bound on latency and traffic. The protocol modeling approach relies on cycle-accurate simulation models in which components can access instantaneously and transparently internal states of other components. Using this strategy, the access time and the traffic due to cache misses are taken into account as it would be on a multiprocessor system without cache coherence. However, the proposed approach still ensures that processors receive coherent data. We detail the implementation of this approach in a cycle accurate multiprocessor simulation environment. To show its effectiveness, we implement cache and memory models for two coherence protocols both with and without our omniscient cache coherence (OCC) proposal. We show with a formal method that this approach makes it possible to preserve the consistency models implied by the cache coherence protocols, and experimentally that the OCC strategy protocol gives a close lower bound on latency and traffic

show abstract

“…Using the Weibull distribution to characterize the execution time of a task is well-accepted in real-time scheduling literature (e.g.,[65,66]). 9 This assumption is reasonable, as we can assume that the vehicle tracks a constant longitudinal speed through a separate control law.…”

mentioning

confidence: 99%

ROTEC: Robust to Early Termination Command Governor for Systems with Limited Computing Capacity

Hosseinzadeh¹,

Sinopoli²,

Kolmanovsky³

et al. 2022

Preprint

View full text Add to dashboard Cite

A Command Governor (CG) is an optimization-based add-on scheme to a nominal closed-loop system. It is used to enforce state and control constraints by modifying reference commands. This paper considers the implementation of a CG on embedded processors that have limited computing resources and must execute multiple control and diagnostics functions; consequently, the time available for CG computations is limited and may vary over time. To address this issue, a robust to early termination command governor is developed which embeds the solution of a CG problem into the internal states of a virtual continuous-time dynamical system which runs in parallel to the process. This virtual system is built so that its trajectory converges to the optimal solution (with a tunable convergence rate), and provides a sub-optimal but feasible solution whenever its evolution is terminated. This allows the designer to implement a CG strategy with a small sampling period (and consequently with a minimum degradation in its performance), while maintaining its constraint-handling capabilities. Simulations are carried out to assess the effectiveness of the developed scheme in satisfying performance requirements and real-time schedulability conditions for a practical vehicle rollover example.

show abstract

Intra- and inter-processor hybrid performance modeling for MPSoC architectures

Cited by 6 publications

References 12 publications

Conservative application-level performance analysis through simulation of MPSoCs

Conservative application-level performance analysis through simulation of MPSoCs

Evaluation of the implementation cost of cache coherence protocols using omniscient actions

ROTEC: Robust to Early Termination Command Governor for Systems with Limited Computing Capacity

Contact Info

Product

Resources

About