Intrinsic Cu gettering at a thermally grown SiO2/Si interface

Bai, P.; Yang, G.‐R.; Lu, Toh‐Ming

doi:10.1063/1.346383

Cited by 16 publications

(6 citation statements)

References 22 publications

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“…The oxide layer in our test structures was intentionally chosen thicker than that in typical production wafers in order to separate metal diffusion profiles and equilibrium metal concentration within the oxide from metals accumulated at Si/SiO 2 interfaces. Such accumulations were observed under certain conditions in copper-and iron-contaminated wafers in the past [14][15][16][17][18][19], and are also visible in our experimental data plotted in figure 4.…”

Section: Experimental: Diffusivity and Segregation Coefficient Of Fe ...supporting

confidence: 78%

Gettering in silicon-on-insulator wafers: experimental studies and modelling

Istratov¹,

Väinölä²,

Huber³

et al. 2005

Semicond. Sci. Technol.

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Buried oxide, which separates the device area from the substrate in silicon-on-insulator (SOI) wafers, forms a diffusion barrier for transition metals in silicon. The impact of this barrier on the efficiency of traditional gettering techniques for iron and copper is evaluated using computer modelling. Several parameters essential for the modelling, such as the diffusivity of iron in SiO 2 and the segregation coefficient of iron and copper in SiO 2 , are verified experimentally. It is found that all available data for the diffusivity of iron in SiO 2 (including data points from the literature and our own value of 1.4 × 10 −13 cm s −2 at 1100 • C) could be fitted by the equation D(Fe in SiO 2 ) = 2.2 × 10 −2 × exp(−3.05 eV/k B T ) (cm 2 s −1 ). The solubility of iron in silicon dioxide was found to be 4.5 times to 5.5 times less than that in silicon at temperatures from 1020 • C to 1100 • C, which indicates that iron does not segregate in SiO 2 . The solubility of Cu in silicon dioxide was determined to be half of that in silicon at 1150 • C and 3.3 times higher than in silicon at 690 • C. Modelling of gettering using these parameters revealed that buried oxide prevents iron from diffusing to gettering sites in the substrate at typical processing temperatures, thus rendering the substrate gettering techniques inefficient. On the other hand, the diffusion barrier protects the device area from contamination from the backside of the wafer. Copper has sufficiently high diffusivity in SiO 2 to diffuse through the buried oxide within a short time at 1000 • C; however, it may be difficult to remove copper from the device area because heavily doped areas of the devices could provide competitive gettering sites for copper. Possible gettering strategies for the SOI wafers are discussed.

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Section: Experimental: Diffusivity and Segregation Coefficient Of Fe ...supporting

confidence: 78%

Gettering in silicon-on-insulator wafers: experimental studies and modelling

Istratov¹,

Väinölä²,

Huber³

et al. 2005

Semicond. Sci. Technol.

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“…It was reported that due to oxidation, the intrinsic Cu gettering occurred at the thermally grown SiO 2 /Si interface. 19 Another possibility for Cu incorporation may arise from the problem of the instrument in this study. The VN barrier and subsequent Cu layer were sputter-deposited in the same chamber, as already described, resulting in the occurrence of an extremely small amount of pre-existing Cu at the surface of SiO 2 .…”

Section: Application Of a Thin Vn Barrier In Cu/ Siomentioning

confidence: 99%

Application of thin nanocrystalline VN film as a high-performance diffusion barrier between Cu and SiO2

Takeyama

Itoi

Satoh

et al. 2004

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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Thin nanocrystalline vanadium nitride (VN) films of low resistivity were examined as an extremely thin diffusion barrier to provide thermal stability in Cu∕VN∕SiO2∕Si systems. A 10-nm-thick VN barrier with grains ranging from several to ∼10nm in diameter provided excellent barrier properties. After annealing at 600°C for 1h, the barrier showed scarcely any change in structure and absence of Cu diffusion and/or decisive interfacial reaction in the system. This was interpreted to mean that the present barrier, which is made of a thermochemically stable δ-VN compound phase with a slightly nitrogen-rich composition and a nanocrystalline structure, was preferable to suppress the solid-phase reaction and/or diffusion, as well as the structural change upon annealing. It was revealed that the nanocrystalline VN barrier is an excellent candidate as a barrier in a forthcoming Cu metallization scheme.

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“…Bai et al demonstrated that copper is gettered to the Si/SiO 2 interface during thermal growth of a silicon oxide layer. 20 Strained Si would also be a possible getter site but only if the silicon lattice is under tensile strain. 16 The molecular volume of the oxide precipitate is larger than the molecular volume of Si.…”

mentioning

confidence: 99%

Investigation of the Copper Gettering Mechanism of Oxide Precipitates in Silicon

Kissinger

Kot

Klingsporn

et al. 2015

ECS J. Solid State Sci. Technol.

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One of the reasons why the principal gettering mechanism of copper at oxide precipitates is not yet clarified is that it was not possible to identify the presence and measure the copper concentration in the vicinity of oxide precipitates. To overcome the problem we used a 14.5 nm thick thermal oxide layer as a model system for an oxide precipitate to localize the place where the copper is collected. We also analyzed a plate-like oxide precipitate by EDX and EELS and compared the results with the analysis carried out on the oxide layer. It is demonstrated that both the interface between the oxide precipitate being SiO 2 and the silicon matrix and the interface between the thermal oxide and silicon consist of a 2-3 nm thick SiO layer. As the results of these experiments also show that copper segregates at the SiO interface layer of the thermal oxide it is concluded that gettering of copper by oxide precipitates is based on segregation of copper to the SiO interface layer.

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Intrinsic Cu gettering at a thermally grown SiO2/Si interface

Cited by 16 publications

References 22 publications

Gettering in silicon-on-insulator wafers: experimental studies and modelling

Gettering in silicon-on-insulator wafers: experimental studies and modelling

Application of thin nanocrystalline VN film as a high-performance diffusion barrier between Cu and SiO2

Investigation of the Copper Gettering Mechanism of Oxide Precipitates in Silicon

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