Intrinsic doping and gate hysteresis in graphene field effect devices fabricated on SiO₂substrates

Abstract

We have studied the intrinsic doping level and gate hysteresis of graphene-based field effect transistors (FETs) fabricated over Si/SiO(2) substrates. It was found that the high p-doping level of graphene in some as-prepared devices can be reversed by vacuum degassing at room temperature or above depending on the degree of hydrophobicity and/or hydration of the underlying SiO(2) substrate. Charge neutrality point (CNP) hysteresis, consisting of the shift of the charge neutrality point (or Dirac peak) upon reversal of the gate voltage sweep direction, was also greatly reduced upon vacuum degassing. However, another type of hysteresis, consisting of the change in the transconductance upon reversal of the gate voltage sweep direction, persists even after long-term vacuum annealing at 200 °C, when SiO(2) surface-bound water is expected to be desorbed. We propose a mechanism for this transconductance hysteresis that involves water-related defects, formed during the hydration of the near-surface silanol groups in the bulk SiO(2), that can act as electron traps.

Giant Dirac point shift of graphene phototransistors by doped silicon substrate current

“…The drain-source current is controlled by the back-gate voltage, and bi-polar characteristics with a Dirac point are produced. The electrical properties of the graphene are significantly influenced by its surrounding environment, e.g., the atmosphere, molecules adsorbed on the SiO 2 layer underneath the graphene, [14][15][16] and the oxide interlayer between the metal electrode and graphene. [17][18][19] For instance, water (H 2 O) molecules adsorbed on the graphene surface cause hysteresis in the electrical properties of the transistor.…”

Influence of post-annealing on the off current of MoS2 field-effect transistors

“…Many reports have announced that the annealing process is dispensable for improving the electrical property of various FETs using original IV semiconductors [29], oxide semiconductors [30,31], layered semiconductors [32][33][34], etc. In the case of 4H-SiC included in the original IV, the annealing process created a passivation layer at the interface, and device parameters were improved, such as the electron mobility and subthreshold swing (SS).…”

Hysteresis modeling in graphene field effect transistors

“…Hysteresis is observed in graphene field effect transistors (GFETs) of many types, including exfoliated flakes, 4,15 transferred large area layers on SiO 2 and SiO 2 /Si 3 N 4 , 16 and as-grown layers SiC grown by chemical vapour deposition (CVD) 17 and sublimation. In this work, a drain hysteresis of similar character is clearly seen in H-intercalated CVD bilayer GFETs when measuring the drain current (i d ) as a function of gate voltage (v g ).…”