Introducing a technology index concept and optimum performance design procedure for single-electron-device based circuits

Sharifi, Mohammad Javad; Bahrepour, Davoud

doi:10.1016/j.mejo.2011.04.014

Cited by 9 publications

(8 citation statements)

References 18 publications

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“…Using the introduced optimization methods in Ref. [41] leads to the presentation of the optimized designs. As a future work the performance of the proposed design shall be optimized.…”

Section: Discussionmentioning

confidence: 99%

High Speed Full Adder Based on Modified Linear Threshold Gate and Its Application to a 4–2 Compressor

Bahrepour¹,

Sharifi²

2013

Jnl of Comp & Theo Nano

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This paper presents a modification for linear threshold gate (LTG) which belongs to the singleelectron-devices (SEDs) family. LTG enables the implementation of any linearly separable Boolean function, however, the modified LTG structure can be utilized as a multi-threshold structure. Based on proposed modified LTG structure, a novel three-input XOR gate design is presented. Then this gate is utilized in designing novel high speed full adder circuit. Since the proposed full adder has internal buffers, it is able to restore the received signals and therefore can be employed in cascaded circuit designs without fan-out concerns. The switching delay and energy consumption of the proposed full adder are analyzed and compared with previously introduced designs. The comparisons show that the proposed full adder has the shortest delay in comparison with other proposed SED full adders. Finally, a 4-2 compressor based on the proposed high speed full adder is introduced as an applicable example.

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“…Using the introduced optimization methods in Ref. [41] leads to the presentation of the optimized designs. As a future work the performance of the proposed design shall be optimized.…”

Section: Discussionmentioning

confidence: 99%

High Speed Full Adder Based on Modified Linear Threshold Gate and Its Application to a 4–2 Compressor

Bahrepour¹,

Sharifi²

2013

Jnl of Comp & Theo Nano

Self Cite

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“…In the other words, comparison of two SEB designs, which are implemented in two different technologies, is not valid unless the two circuits are scaled into a single technology. Therefore, we need an index for SED technology [17].…”

Section: Optimizing Digital Logic Not Gatementioning

confidence: 99%

“…This index demonstrates the most important limitations of the technology in an appropriate manner due the fact that it has a clear relation with MOSFET circuit performances. For SED based circuits and regarding the two technology index specifications [17], the total capacitor of the island, C T , and the tunneling resistor, R T , are introduced as a technology index. C T includes the possibility of miniaturization and R T defines the technology's manufacturing tolerance.…”

Section: Optimizing Digital Logic Not Gatementioning

confidence: 99%

“…However, it does not change the logic function. As mentioned for achieving better performance, NOT gate circuit design is improved by the use of scaling process [17]. The scaling process needs two main parameters named scaling factors.…”

Section: Optimizing Digital Logic Not Gatementioning

confidence: 99%

“…In many cases designers propose a circuit and evaluate them by simulation software. While after introducing a digital application for a SED based circuit design optimization is the next challenge [17]. In the following section, the previously proposed SEB based NOT gate is optimized.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Area efficient digital logic NOT gate using single electron box (SEB)

Bahrepour

2017

Int. J. Simul. Multisci. Des. Optim.

Self Cite

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-The continuing scaling down of complementary metal oxide semiconductor (CMOS) has led researchers to build new devices with nano dimensions, whose behavior will be interpreted based on quantum mechanics. Singleelectron devices (SEDs) are promising candidates for future VLSI applications, due to their ultra small dimensions and lower power consumption. In most SED based digital logic designs, a single gate is introduced and its performance discussed. While in the SED based circuits the fan out of designed gate circuit should be considered and measured. In the other words, cascaded SED based designs must work properly so that the next stage(s) should be driven by the previous stage. In this paper, previously NOT gate based on single electron box (SEB) which is an important structure in SED technology, is reviewed in order to obtain correct operation in series connections. The correct operation of the NOT gate is investigated in a buffer circuit which uses two connected NOT gate in series. Then, for achieving better performance the designed buffer circuit is improved by the use of scaling process.

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A general SPICE compatible circuit model for single‐electron devices and application to bit‐error‐rate calculations

Sharifi

Jamshidnezhad

2013

Circuit Theory & Apps

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The main purpose of this paper is study of the single‐electron devices (SEDs) behavior, having metal islands, in the time domain. On this basis, some new conceptions, such as division of islands in independent type and dependent type and introduction of multi‐dimensional state space for a SED, have been presented. Then, a new circuit model is introduced for SEDs in general N‐dimensional case. This model is based on the orthodox theory and the solution of the time‐dependent master equation with the capability of installation in the HSPICE software. Hence, one can simulate behavior of the compound circuits including SEDs and other circuit elements by help of this model. Another interesting characteristic of the introduced circuit model is the possibility of using it in calculation of bit error rate in single‐electron logical gates considering both the time and the temperature effects. The behavior of various SEDs in low frequencies is studied, and the results are compared with the results of SIMON, often used as a reference. Furthermore, the time‐dependent results of these devices in high frequencies are calculated and compared with the analytic results for step inputs. These comparisons indicate accuracy and validity of the model. Finally, the model is used for simulating time‐dependent behavior of some single‐electron logic gates, and their total error rate are calculated. Copyright © 2013 John Wiley & Sons, Ltd.

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Introducing a technology index concept and optimum performance design procedure for single-electron-device based circuits

Cited by 9 publications

References 18 publications

High Speed Full Adder Based on Modified Linear Threshold Gate and Its Application to a 4–2 Compressor

High Speed Full Adder Based on Modified Linear Threshold Gate and Its Application to a 4–2 Compressor

Area efficient digital logic NOT gate using single electron box (SEB)

A general SPICE compatible circuit model for single‐electron devices and application to bit‐error‐rate calculations

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