This paper presents an EDA (Electronic Design Automation) tool that generates basic building blocks for cryptographic hardware in VHDL. The purpose of the tool is to decrease the design time of cryptographic hardware and to allow designers to make abstraction of both the arithmetic and design complexity. The tool generates multiple implementations for one arithmetic description and then benchmarks the implementations to find the most optimal, based upon design space parameters. These parameters consist of area and speed requirements. We present datapath and control logic results for a Xilinx Virtex-5 FPGA.The novelty in our approach lies in the fact that we exploit the higher-order features of functional languages to facilitate the design space exploration and that we take benefit from the strength of the third-party synthesis tool by generating VHDL code at an abstraction level that is higher than the gate level. Nevertheless, in this stage of the development of the tool, the different cryptographic architectures are hand-made and the selection of the most optimal solution, based upon user requirements, is done by exhaustive search. This means that the tool leaves room for improvement, but forms a solid base for further development.
MOTIVATION AND CONTRIBUTIONIn storage and communication of digital data, security is an important issue. To provide confidentiality, authentication, secure key exchange, privacy, . . . cryptographic algorithms are needed. When requirements such as high speed, low area, low power consumption and/or high security level are an issue, these cryptographic algorithms are implemented in hardware coprocessors. Most of the times cryptographic hardware needs to be designed with as little overhead as possible because it does not contribute to the core functionality of the application. However, to achieve a sufficient level of security, cryptographic algorithms and in particular public * Davy Wolfs was funded by BOF project CREA/09/016 of the Katholieke Universiteit Leuven. key algorithms consist of rather complicated mathematical operations on large numbers. Consequently, the challenge for the design of cryptographic hardware is to find a suitable architecture for a rather complicated mathematical operation on large numbers that results in a restricted overhead in time, area and/or power consumption.Like almost all digital designs, a cryptographic hardware architecture consists of a datapath and control logic. In this paper, we explore the design space of both. We are specifically interested in the area and speed of the actual hardware after synthesis by both FPGA and ASIC (commercial) third-party tools. Therefore we make sure that the VHDL code generated by our Lava programs is platformindependent. We also shift from basic logic gates to formal FSMs for the description of the control path, as is common in VHDL programming. These state machines can be simulated in Haskell, and exported to native VHDL FSM code on the behavioral level, which gives more optimization possibilities to the synthesis ...