Introducing the IA-64 architecture

Huck, Jerry; Morris, Dale; Ross, Jonathan; Knies, Allan; Mulder, H.; Zahir, Rumi

doi:10.1109/40.877947

Cited by 95 publications

(53 citation statements)

References 6 publications

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“…Instruction power reduction for VLIW processors has been extensively studied due to the large width of the instructions and the frequency of NOPs for various functional units [4], [8]. Approaches have included instruction compression and scheduling to minimize the instruction bus activity factor [5].…”

Section: Related Workmentioning

confidence: 99%

Hierarchical Instruction Register Organization

Black-Schaffer

Balfour

Dally

et al. 2008

IEEE Comput. Arch. Lett.

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Abstract-This paper analyzes a range of architectures for efficient delivery of VLIW instructions for embedded media kernels. The analysis takes an efficient Filter Cache as a baseline and examines the benefits from 1) removing the tag overhead, 2) distributing the storage, 3) adding indirection, 4) adding efficient NOP generation, and 5) sharing instruction memory. The result is a hierarchical instruction register organization that provides a 56% energy and 40% area savings over an already efficient Filter Cache.Index Terms-energy-efficient embedded processor architecture, hierarchical and distributed instruction register organization, VLIW instruction delivery

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Section: Related Workmentioning

confidence: 99%

Hierarchical Instruction Register Organization

Black-Schaffer

Balfour

Dally

et al. 2008

IEEE Comput. Arch. Lett.

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“…Figure 4 shows a use of this simplified SiMulPro core. The right hand side is characteristic of the Multiflow [6], and the EPIC architecture [16], which led to the I-64 [11] and the Itanium [17]. The Mill computer [7] bears some resemblance to the left hand side, but has only two instruction pointers.…”

Section: Application Compatibilitymentioning

confidence: 99%

Core Module Optimizing PDE Sparse Matrix Models With HPCG Example

Jennings¹

2017

JSFI

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This paper introduces a fundamentally new computer architecture for supercomputers. The core module is application compatible with an existing superscalar microprocessor, with minimized energy use, and is optimized for local sparse matrix operations. Optimized sparse matrix manipulation is discussed by analyzing the High Performance Conjugate Gradient (HPCG) benchmark specification. This analysis shows how the DRAM memory wall is removed for this benchmark, and for sparse matrix models of partial differential equations (PDEs) for a wide cross section of applications. By giving the programmer improved control over the configuration of the supercomputer, the potential for communication problems is minimized. Application compatibility is achieved while removing the superscalar instruction interpreter and multi-thread controller from the existing microprocessor's hardware. These are transformed into compile-time utilities. The instruction cache is removed through an innovation in VLIW instruction processing. The data caches are unnecessary and are turned off in order to optimally implement sparse matrix models.

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“…Using Itanium T M architecture [9,8] software pipelining features (such as predication [12], register rotation [5], and epilog stage count register), these methods can be implemented with minimal code changes. The inner loop schedule remains unchanged and only a few additional instructions are added to the outer loop.…”

Section: (A)mentioning

confidence: 99%

“…The Itanium T M architecture provides many features to aid the compiler in enhancing and exploiting instruction level parallelism (ILP) [9,8]. These include an explicitly parallel (EPIC) instruction set, large register files, register renaming, predication [12], speculation [11], and special support for software pipelining.…”

Section: Software Pipelining In the Itanium T M Architecturementioning

confidence: 99%

Software Pipelining of Nested Loops

Muthukumar

Doshi

2001

Lecture Notes in Computer Science

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Abstract. Software pipelining is a technique to improve the performance of a loop by overlapping the execution of several iterations. The execution of a software-pipelined loop goes through three phases: prolog, kernel, and epilog. Software pipelining works best if most of the time is spent in the kernel phase rather than in the prolog or epilog phases. This can happen only if the trip count of a pipelined loop is large enough to amortize the overhead of prolog and epilog phases. When a softwarepipelined loop is part of a loop nest, the overhead of filling and draining the pipeline is incurred for every iteration of the outer loop. This paper introduces two novel methods to minimize the overhead of softwarepipeline fill/drain in nested loops. In effect, these methods overlap the draining of the software pipeline corresponding to one outer loop iteration with the filling of the software pipeline corresponding to one or more subsequent outer loop iterations. This results in better instructionlevel parallelism (ILP) for the loop nest, particularly for loop nests in which the trip counts of inner loops are small. These methods exploit Itanium T M architecture software pipelining features such as predication, register rotation, and explicit epilog stage control, to minimize the code size overhead associated with such a transformation. However, the key idea behind these methods is applicable to other architectures as well. These methods have been prototyped in the Intel optimizing compiler for the Itanium T M processor. Experimental results on SPEC2000 benchmark programs are presented.

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Introducing the IA-64 architecture

Cited by 95 publications

References 6 publications

Hierarchical Instruction Register Organization

Hierarchical Instruction Register Organization

Core Module Optimizing PDE Sparse Matrix Models With HPCG Example

Software Pipelining of Nested Loops

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