Introduction and Analysis of Optimal Routing Algorithm in Benes Networks

Karimi, Abbas; Aghakhani, Kiarash; Manavi, Seyed Ehsan; Zarafshan, Faraneh; Al-Haddad, S. A. R.

doi:10.1016/j.procs.2014.11.068

Cited by 11 publications

(7 citation statements)

References 14 publications

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“…There are many other algorithms that route Benes networks [21,29,30]; however, essentially, they are all variations of the aforementioned ones. The solution presented in [31] is the closest, in terms of function, to the solution covered in this paper. Even though it is one of the solutions that use two-dimensional (2D) matrixes, in some instances, it produces the same switch setting.…”

Section: Introductionmentioning

confidence: 91%

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Novel Benes Network Routing Algorithm and Hardware Implementation

et al. 2022

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Benes/Clos networks constitute a particularly important part of interconnection networks and have been used in numerous areas, such as multi-processor systems, data centers and on-chip networks. They have also attracted great interest in the field of optical communications due to the increasing popularity of optical switches based on these architectures. There are numerous algorithms aimed at routing these types of networks, with varying degrees of utility. Linear algorithms, such as Sun Tsu and Opferman, were historically the first attempt to standardize the routing procedure of this types of networks. They require matrix-based calculations, which are very demanding in terms of resources and in some cases involve backtracking, which impairs their efficiency. Parallel solutions, such as Lee’s algorithm, were introduced later and provide a different answer that satisfy the requirements of high-performance networks. They are, however, extremely complex and demand even more resources. In both cases, hardware implementations reflect their algorithmic characteristics. In this paper, we attempt to design an algorithm that is simple enough to be implemented on a small field programmable gate array board while simultaneously efficient enough to be used in practical scenarios. The design itself is of a generic nature; therefore, its behavior across different sizes (8 × 8,16 × 16,32 × 32,64 × 64) is examined. The platform of implementation is a medium range FPGA specifically selected to represent the average hardware prototyping device. In the end, an overview of the algorithm’s imprint on the device is presented alongside other approaches, which include both hard and soft computing techniques.

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Section: Introductionmentioning

confidence: 91%

“…Considering the fact that this is a linear algorithm, this is no surprise. One thing that should be mentioned is that in contrast to Opferman's algorithm, there is no backtracking to change the settings of the switches [31].…”

Section: Algorithmmentioning

confidence: 99%

Novel Benes Network Routing Algorithm and Hardware Implementation

et al. 2022

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“…By loading the states from the LUT and setting up the switches accordingly, the input light could be routed to the target position. The switches states of all possible operands will be pre-calculated and stored in the LUT by using the division algorithm [28]. This algorithm claims that it is the optimal one to route a Benes network form outermost stages to the central one.…”

Section: Integrated Photonic Residue Adder and Multipliermentioning

confidence: 99%

DNNARA: A Deep Neural Network Accelerator using Residue Arithmetic and Integrated Photonics

Peng

Alkabani

Sun

et al. 2020

49th International Conference on Parallel Processing - ICPP

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Deep Neural Networks (DNNs) are currently used in many fields, including critical real-time applications. Due to its compute-intensive nature, speeding up DNNs has become an important topic in current research. We propose a hybrid opto-electronic computing architecture targeting the acceleration of DNNs based on the residue number system (RNS). In this novel architecture, we combine the use of Wavelength Division Multiplexing (WDM) and RNS for efficient execution. WDM is used to enable a high level of parallelism while reducing the number of optical components needed to decrease the area of the accelerator. Moreover, RNS is used to generate optical components with short optical critical paths. In addition to speed, this has the advantage of lowering the optical losses and reducing the need for high laser power. Our RNS compute modules use one-hot encoding and thus enable fast switching between the electrical and optical domains. In this work, we demonstrate how to implement the different DNN computational kernels using WDM-enabled RNS based integrated photonics. We provide an accelerator architecture that uses our designed components and perform design space exploration to select efficient architecture parameters. Compared to memristor crossbars, our residue matrix-vector multiplication unit has two orders of magnitude higher peak performance. Our experimental evaluation using DNN benchmarks illustrates that our architecture can perform more than 19 times faster than the state of the art GPUs under the same power budget. CCS CONCEPTS • Computer systems organization → Neural networks; Optical computing; • Computing methodologies → Parallel computing methodologies.

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“…Figure 9 shows the complete Benes network. The following Figure 11 is an example of route change in each switching element to connect input -output pairs of 0-3, 1-0, 2-7, 3-1, 4-4, 5-6, 6-2, 7-5 by using division routing algorithm [8]. By using the same input-output pairs the route arrangement can be refigures as in Figure 12.…”

Section: Benes Multistage Switchingmentioning

confidence: 99%

“…This re-routing process requires routing algorithms which were proposed by many researchers. Looping procedure was proposed by [5], parallel routing was proposed by [6], matrix based algorithm was proposed by [7], and division routing algorithm and input/output algorithm proposed in [8]. The drawback is, Benes network needs a complex control to accommodate new calls [9].…”

Section: Introductionmentioning

confidence: 99%

Cross-Point Comparison of Multistage Non-Blocking Technologies

Zulfin¹,

Suherman²,

Fauzi³

et al. 2018

IJET

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Multistage switching networks play important role in communication and computer network. They make communication nodes connect to each other. In computer hardware switches connect processors and memories. Initially, switches are arranged as one stage interconnection. As clients are growing, multistage is a must. The finding Clos multistage switching initiated multistage technologies. Benes improves Clos by reducing number of cross-points by using a 2 x 2 switch element and call re-routing. Batcher improves the technology by other way which is sorting destination address. Banyan is then joined to Batcher to simplify routing control. This paper analyses the number of cross-point required in Clos, Benes and Batcher Banyan to accomplish multistage switching architecture of 16, 64, 256, 1024 and 2048 input/output ports. As results, Clos cross-point is in averages 495.24% higher than Benes and 160.30% higher than Batcher Banyan. Clos blocking probabilities are closed to zero. Benes blocking probabilities are conditionally zero. Batcher Banyan blocking probabilities are zero.

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Introduction and Analysis of Optimal Routing Algorithm in Benes Networks

Cited by 11 publications

References 14 publications

Novel Benes Network Routing Algorithm and Hardware Implementation

Novel Benes Network Routing Algorithm and Hardware Implementation

DNNARA: A Deep Neural Network Accelerator using Residue Arithmetic and Integrated Photonics

Cross-Point Comparison of Multistage Non-Blocking Technologies

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