Introduction to the wire-speed processor and architecture

Franke, Hubertus; Xenidis, Jimi; Basso, Carla de Almeida Martins; Bass, Brian; Woodward, Sandra; Brown, Jeff; Johnson, C. L.

doi:10.1147/jrd.2009.2036980

Cited by 70 publications

(46 citation statements)

References 16 publications

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“…The PowerEN Edge of Network processor was recently described by Franke et al [2010]. PowerEN is an interesting architecture for biased-locking because it is an available highly multi-threaded processor with 64 hardware threads.…”

Section: Target Platformsmentioning

confidence: 99%

Fast asymmetric thread synchronization

Cleary

Callanan

Purcell

et al. 2013

ACM Trans. Archit. Code Optim.

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For most multi-threaded applications, data structures must be shared between threads. Ensuring thread safety on these data structures incurs overhead in the form of locking and other synchronization mechanisms. Where data is shared among multiple threads these costs are unavoidable. However, a common access pattern is that data is accessed primarily by one dominant thread, and only very rarely by the other, non-dominant threads. Previous research has proposed biased locks, which are optimized for a single dominant thread, at the cost of greater overheads for non-dominant threads. In this paper we propose a new family of biased synchronization mechanisms that, using a modified interface, push accesses to shared data from the non-dominant threads to the dominant one, via a novel set of message passing mechanisms. We present mechanisms for protecting critical sections, for queueing work, for caching shared data in registers where it is safe to do so, and for asynchronous critical section accesses. We present results for the conventional Intel R Sandy Bridge processor and for the emerging network-optimized many-core IBM R PowerEN TM processor. We find that our algorithms compete well with existing biased locking algorithms, and, in particular, perform better than existing algorithms as accesses from non-dominant threads increase.

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Section: Target Platformsmentioning

confidence: 99%

Fast asymmetric thread synchronization

Cleary

Callanan

Purcell

et al. 2013

ACM Trans. Archit. Code Optim.

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“…On the Cell, FSM-based solutions for exact matching include: a register-file-based solution by Iorio The IBM Power Edge of Network (PowerEN) processor is a modern multi-core system with several specialized accelerators, including an accelerator for regular expression matching [11,20]. In our classification, the accelerators are memory bus-attached to the main processing cores (PowerBus-attached, to be more precise) and deliver regex processing bandwidth in the range of I/O bus-and networkattached accelerators.…”

Section: Related Workmentioning

confidence: 99%

Accelerating business analytics applications

Salapura

Karkhanis

Nagpurkar

et al. 2012

IEEE International Symposium on High-Performance Comp Architecture

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Business text analytics applications have seen rapid growth, driven by the mining of data for various decision making processes. Regular expression processing is an important component of these applications, consuming as much as 50% of their total execution time. While prior work on accelerating regular expression processing has focused on Network Intrusion Detection Systems, business analytics applications impose different requirements on regular expression processing efficiency. We present an analytical model of accelerators for regular expression processing, which includes memory bus-, I/O bus-, and networkattached accelerators with a focus on business analytics applications. Based on this model, we advocate the use of vector-style processing for regular expressions in business analytics applications, leveraging the SIMD hardware available in many modern processors. In addition, we show how SIMD hardware can be enhanced to improve regular expression processing even further. We demonstrate a realized speedup better than 1.8 for the entire range of data sizes of interest. In comparison, the alternative strategies deliver only marginal improvement for large data sizes, while performing worse than the SIMD solution for small data sizes.

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“…The PowerEN TM "Edge of Network" processor (also known as WireSpeedProcessor) [8,10] was recently introduced by IBM. It integrates technologies from both server and network processors to address the domain of network facing applications where latency and throughput are the primary design targets.…”

Section: Poweren Tm Processormentioning

confidence: 99%

Ultra low latency market data feed on IBM PowerENTM

et al. 2011

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Financial Market IT solutions increasingly depend on ultra low latency message processing and target microseconds latencies in order to provide traders with a competitive advantages over their peers. Some solutions are available on the market, ranging from general purpose systems with advanced network cards to specialized hardware solutions based on FPGA. The novel IBM PowerEN TM "Edge of Network" processor integrates network interfaces with functional accelerators and multi-threaded cores. This paper describes the design, implementation and performance evaluation of a Market Data Feed solution based on the PowerEN processor. The paper details the SoC mechanism designed to reduce latency and increase throughput and shows how these can be used to build a Market Data Feed solutions that achieves performance figures usually obtainable only by special hardware. This prototype described achieves an average latency of 6.7 µs for an OPRA v2 feed and is able to process 1M updates per second on 2 hardware thread, achieving more than 16M updates per second on a single chip solution without consuming all the resources and thus being able to also run customer software.

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Introduction to the wire-speed processor and architecture

Cited by 70 publications

References 16 publications

Fast asymmetric thread synchronization

Fast asymmetric thread synchronization

Accelerating business analytics applications

Ultra low latency market data feed on IBM PowerENTM

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