Introspection Mechanisms for Semi-Formal Verification in a System-Level Design Environment

Exploring the design space when constructing a system is vital to realize a well performing design. Design complexity has made building high-level system models to explore the design space an essential but time-consuming and tedious part of the system design. Reduction in design time and acceleration of design exploration can be provided through reusing IP-cores to construct system models. As a result, it is common to have high-level SoC design flow based on IP libraries promoting reuse. However, the success of these would be dependent on how introspection and reflection capabilities are provided as well as what are the interoperability standard defined. This leads to the important question of what kind of IP metadata must be available to allow CAD tools to effectively manipulate these designs as well as allow for a seamless integration and exchange design information between tools and design flows. In this article, we describe our tools and methodology, which allow introspection of SystemC designs, such that the extracted metadata enables IP composition. We discuss the issues related to extraction of metadata from IPs specified in SystemC and show how our methodology combines C++ and XML parsers and data structures to achieve the above.

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“…Some of these are SystemPerl [23], EDG [10], SystemCXML [3,4], Pinapa [19], KaSCPar [11], and ESys.NET [16].…”

Section: Reflection and Introspection Techniquesmentioning

confidence: 99%

“…ESys.NET [13,16] is a system level modeling and simulation environment using the .NET framework [17] and C# language [18]. They employ the inherent introspective capabilities in the .NET framework to achieve their objective.…”

Section: Reflection and Introspection Techniquesmentioning

confidence: 99%