Invariants for Distributed Local Control Elements of a New Synchronous Bit-Serial Architecture

Proceedings of the 20th Annual Conference on Integrated Circuits and Systems Design

Weber

2007

This paper presents latency optimizations for a specific hardware architecture, which was developed based on the combination of different design paradigms and thus requires sophisticated design optimizations. The architecture comprises synchronous and systematic bit-serial processing without a central controlling instance. It was recently patented and targets future high-speed applications due to the abdication of long wires. So-called routers, achieving a reconfigurable system, can overcome the application specificity of the basic version of the architecture. This paper focuses on the challenge of latency optimizations also covering data synchronization problems when implementing the architecture. We propose and evaluate several variations for the realization.

Section: Mact Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Optimization techniques for a reconfigurable, self-timed, and bit-serial architecture

Dittmann

Proceedings of the 20th Annual Conference on Integrated Circuits and Systems Design

Weber

2007

Section: Mact Architecturementioning

confidence: 99%

Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture

Giefers

Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design

2006

In this paper, we present an approach for low-power driven synthesis based on local frequency/voltage scaling. During the scheduling phase of the High-Level Synthesis (HLS) the design is partitioned into different frequency/voltage islands. Operators within these islands, are encapsulated by wrappers to ensure correct dataflow between the islands. A wrapper consists of a clock generator and input-and output ports. The local clocks are calculated by dividing the global clock signal. With the developed wrappers we are able to automatically integrate local frequency/voltage scaling for our target architecture by our HLS tool. As an example we implement the inverse discrete cosine transformation (IDCT).

“…Strict categorization helps us to distinguish possible cases and to develop solutions for the high level synthesis of such elements. Thereby, we can fall back on an * This work was partly funded by the Deutsche Forschungsgemeinschaft (DFG) in SPP 1148 already realized high level synthesis for the architecture [3,5], which automatically generates MACT implementations in VHDL out of data flow graphs. In the high level synthesis, we avoid deadlocks and establish the local control mechanism of the MACT architecture.…”

Section: Introductionmentioning

confidence: 99%

Towards the Implementation of Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture

Dittmann

2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006)

Weber

2006

This paper develops path concepts for the execution of different algorithms on a reconfigurable architecture. New architecture concepts demand for permanent evaluation of such extensions, also including validating case studies. The recently patented synchronous bit-serial pipelined architecture, which we investigate in this paper, comprises synchronous and systematic bit-serial processing without a central controlling instance. It targets future high speed applications due to the abdication of long wires. The application specificity of the basic version of the architecture can be overcome by so called routers, achieving a reconfigurable system. This paper focuses on the difficulty to conceptualize these routers and proposes several variations for implementation. The case study, which comprises a combined version of the FDCT/IDCT algorithm, serves as an application example for the reconfigurability of the architecture.