Inverting amplifier based ultra low power low offset current comparator

Memristors are intensively proposed in many applications, such as biosensors and machine learning. Regarding their analog characteristics, memristance decoder is, therefore, an essential part for every memristor-based system. As memristor is a temperature sensitive device, this work proposes a memristance decoder circuit with self-temperature calibration. Its main building block is a comparator which is based on current mode circuit to achieve high performance at low power. The design provides configurable precision based on the available energy and supports both synchronous and asynchronous schemes. Moreover, the VTEAM model is modified to include the temperature effect on the memristance in the analysis. The simulation results, based on UMC 65nm low-leakage CMOS technology, show the following comparator's characteristics: 1.70% maximum offset, 2.91ns worst case latency, 343M Hz maximum frequency and 48.79f J maximum energy per comparison. Monte Carlo simulation shows the metastable state in determining the memristor value. This can be solved by extending the clock period or applying a metastability resolver. The proposed memristor model reveals that memristance at high resistive state degrades quadratically with the rise of the temperature and at 85°C nearly reaches the memristance of low resistive state. The possibility of decoding error due to the temperature effect is demonstrated via simulations.

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“…Therefore, it is not suitable for low-power applications. This is the common issue of any static comparators such as the works in [56] and [57].…”

Section: Discussionmentioning

confidence: 99%

“…Static current comparators which indicate the direction of the input current are proposed in [56], [57]. The work in [56] employs a flipped voltage follower to lower the input impedance while [57] supports near-threshold operation with zero input offset. Nevertheless, their latency are very long, especially for [56].…”

Section: Discussionmentioning

confidence: 99%

Toward Designing Thermally-Aware Memristance Decoder

Bunnam

Soltan

Sokolov

et al. 2019

IEEE Trans. Circuits Syst. I

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“…Inverting amplifier-based ultra-low power low offset current comparator is discussed in [16,20]. In this proposed method an identical inverting amplifier is introduced to produce the low-input offset current in a comparator.…”

Section: Literature Workmentioning

confidence: 99%

High resolution mutated dynamic precision power gated comparator for 9-bit SAR ADC

Thamaraimanalan¹,

Venkatesan

2022

Preprint

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Comparator design is a major challenge during the implementation of high resolution SAR ADCs. In this research, a mutated dynamic power gated comparator is designed to achieve the SAR ADC with ultra-low power and enhanced gain. The proposed power gated comparator is designed using 45nm CMOS technology, and it is tested at 3.3V and 5V. High speed and low power are achieved through transistor sizing and power gating techniques. Mismatch of transistors, the offset value is appropriately calculated using the input resistance of the differential amplifier and trans conductance. Also, the offset cancellation and digital calibration techniques are included in the design to enhance the precision, and to improve the performance of ADCs. For the proposed comparator, phase margin, gain, ICMR, power consumption, offset voltage, slew rate, load capacitance, propagation delay, kickback noise, and settling time are compared with the conventional comparator. The proposed design consumes only 4.2mW while operating at 5V and 1.5mW when the input voltage is 3.3V. The effective resolution of the SAR ADC is observed as 8.2 bit with the proposed power gated comparator.

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“…However, in the double-tail comparator, the tail current can suppress the offset in the comparison, which arises due to the variation in common mode voltage (Shen et al, 2017). Furthermore, an identical inverting amplifier can be used to produce the low-input offset current in a comparator (Suriyavejwongs et al, 2017).…”

Section: Introductionmentioning

confidence: 99%

Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology

Faheem

Zhong

Wang

et al. 2020

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Purpose Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC. Design/methodology/approach A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET’s and small-sized capacitors in such a way that there is no need for any matching and calibration. Findings The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms. Originality/value The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as “spider-latch”.

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Inverting amplifier based ultra low power low offset current comparator

Cited by 4 publications

References 18 publications

Toward Designing Thermally-Aware Memristance Decoder

Toward Designing Thermally-Aware Memristance Decoder

High resolution mutated dynamic precision power gated comparator for 9-bit SAR ADC

Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology

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