Investigating different general-purpose and embedded multicores to achieve optimal trade-offs between performance and energy

Lorenzon, Arthur F.; Cristina, Márcia; Beck, Antonio Carlos Schneider

doi:10.1016/j.jpdc.2016.04.003

Cited by 21 publications

(8 citation statements)

References 19 publications

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“…Considering only MPI‐1 and MPI‐2, the second one was the one with the worst results. Similar behavior was observed by Lorenzon et al In addition, the pseudo‐applications which presented the worst results for MPI are the only ones who have a higher percentage of memory usage than CPU usage during execution . In this way, we can conclude that memory accesses have a strong negative impact on energy consumption.…”

Section: Resultssupporting

confidence: 83%

“…Using 20 parallel tasks, JA and GS with MPI‐2 run about 2×10 12 of total instructions, against 500×10 9 for MPI‐1 and about 15×10 9 for OpenMP and PThreads. As the work of Lorenzon et al shows, these pseudo‐applications are among those that do a lot of communication among tasks and in MPI this communication is very costly, which increases the number of instructions.…”

Section: Resultsmentioning

confidence: 99%

“…In these studies, the authors classified the pseudo‐applications in such a way that all scenarios analyzed contained at least one pseudo‐application with: high CPU usage and high memory usage; high CPU usage and low memory usage; low CPU usage and high memory usage; or low CPU and memory usage. Finally, Lorenzon et al used some of these pseudo‐applications to verify the best performance and energy consumption in different multicore architectures.…”

Section: Pampar Pseudo‐applicationsmentioning

confidence: 99%

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PAMPAR: A new parallel benchmark for performance and energy consumption evaluation

Garcia

Schepke

Girardi

2019

Concurrency and Computation

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Summary This paper presents PAMPAR, a new benchmark to evaluate the performance and energy consumption of different Parallel Programming Interfaces (PPIs). The benchmark is composed of 11 algorithms implemented in PThreads, OpenMP, MPI‐1, and MPI‐2 (spawn) PPIs. Previous studies have used some of these pseudo‐applications to perform this type of evaluation in different architectures since there is no benchmark that offers this variety of PPIs and communication models. In this work, we measure the energy and performance of each pseudo‐application in a single architecture, varying the number of threads/processes. We also organize the pseudo‐applications according to their memory accesses, floating‐point operations, and branches. The goal is to show that this set of pseudo‐applications has enough features to build a parallel benchmark. The results show that there is no single best case that provides both better performance and low energy consumption in the presented scenarios. Moreover, the pseudo‐applications usage of the system resources are different enough to represent different scenarios and be efficient as a benchmark.

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Section: Resultssupporting

confidence: 83%

Section: Resultsmentioning

confidence: 99%

Section: Pampar Pseudo‐applicationsmentioning

confidence: 99%

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PAMPAR: A new parallel benchmark for performance and energy consumption evaluation

Garcia

Schepke

Girardi

2019

Concurrency and Computation

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“…There are four basic techniques for minimizing power dissipation in embedded electronic systems: voltage scaling, frequency scaling, power gating, and clock gating. As is well known, many theoretical considerations, as well as practical experiments, have shown that the energy consumed by electronic circuits strongly depends on the operating frequency [2,8,9,[15][16][17][18].…”

Section: Related Workmentioning

confidence: 99%

An Analysis of the Impact of Gating Techniques on the Optimization of the Energy Dissipated in Real-Time Systems

Antolak

Pułka

2022

Applied Sciences

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The paper concerns research on electronics-embedded safety systems. The authors focus on the optimization of the energy consumed by multitasking real-time systems. A new flexible and reconfigurable multi-core architecture based on pipeline processing is proposed. The presented solution uses thread-interleaving mechanisms that allow avoiding hazards and minimizing unpredictability. The proposed architecture is compared with the classical solutions consisting of many processors and based on the scheme using one processor per single task. Energy-efficient task mapping is analyzed and a design methodology, based on minimizing the number of active and utilized resources, is proposed. New techniques for energy optimization are proposed, mainly, clock gating and switching-resources blocking. The authors investigate two main factors of the system: setting the processing frequency, and gating techniques; the latter are used under the assumption that the system meets the requirements of time predictability. The energy consumed by the system is reduced. Theoretical considerations are verified by many experiments of the system's implementation in an FPGA structure. The set of tasks tested consists of programs that implement Mälardalen WCET benchmark algorithms. The tested scenarios are divided into periodic and non-periodic execution schemes. The obtained results show that it is possible to reduce the dynamic energy consumed by real-time applications' meeting their other requirements.

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“…IV. METHODOLOGY Benchmarks: We consider ten parallel applications already parallelized from [20], which have different communication demands and operations to exchange data, as depicted in Table I. They are classified into two classes: High Communication (HC) and Low Communication (LC) and were executed with a small input set, used for the learning phase, and a regular input set (Table I), used to evaluate BALDER.…”

Section: B Learning Algorithmmentioning

confidence: 99%

Aging-Aware Parallel Execution

Medeiros

Berned

Navarro

et al. 2021

IEEE Embedded Syst. Lett.

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Computation has been pushed to the edge to decrease latency and alleviate the computational burden of the IoT applications in the cloud. However, the increasing processing demands of Edge Applications make necessary the employment of platforms that exploit thread-level parallelism (TLP). Yet, power and heat dissipation rise as TLP inadvertently increases or when parallelism is not cleverly exploited, which may be the result of the non-ideal use of a given PPI (Parallel Program Interface). Besides the common issues, such as the need for more robust power sources and better cooling, heat also adversely affects aging, accelerating phenomenons such as negative bias temperature instability (NBTI) and hot-carrier injection (HCI), which further reduces processor lifetime. Hence, considering that increasing the lifespan of an edge device is key, so the number of times the application set may execute until its end-of-life is maximized, we propose BALDER. It is a learning framework capable of automatically choosing optimal configuration executions (PPI and number of threads) according to the parallel application at hand, aiming to maximize the trade-off between aging and performance. When executing ten well-known applications on two multicore embedded architectures, we show that BALDER can find a nearly-optimal configuration for all our experiments.

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Investigating different general-purpose and embedded multicores to achieve optimal trade-offs between performance and energy

Cited by 21 publications

References 19 publications

PAMPAR: A new parallel benchmark for performance and energy consumption evaluation

PAMPAR: A new parallel benchmark for performance and energy consumption evaluation

An Analysis of the Impact of Gating Techniques on the Optimization of the Energy Dissipated in Real-Time Systems

Aging-Aware Parallel Execution

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