Abstract-Positive bias stress-induced instability in amorphous indium-gallium-zinc-oxide (a-IGZO) bottom-gate thin-film transistors (TFTs) was investigated under high V GS /low V DS and low V GS /high V DS stress conditions through incorporating a forward/reverse V GS sweep and a low/high V DS readout conditions. Our results showed that the electron trapping into the gate insulator dominantly occurs when high V GS /low V DS stress is applied. On the other hand, when low V GS /high V DS stress is applied, it was found that holes are uniformly trapped into the etch stopper and electrons are locally trapped into the gate insulator simultaneously. During a recovery after the high V GS /low V DS stress, the trapped electrons were detrapped from the gate insulator. In the case of recovery after the low V GS /high V DS stress, it was observed that the electrons in the gate insulator diffuse to a direction toward the source electrode and the holes were detrapped to out of the etch stopper. Also, we found that the potential profile in the a-IGZO bottom-gate TFT becomes complicatedly modulated during the positive V GS /V DS stress and the recovery causing various threshold voltages and subthreshold swings under various read-out conditions, and this modulation needs to be fully considered in the design of oxide TFT-based active matrix organic light emitting diode display backplane.