Investigation and design of ion-implanted MOSFET based on (18 nm) channel length

Abdul-kadir, Firas Natheer; Mohammad, Khalid khaleel; Hashim, Yasir

doi:10.12928/telkomnika.v18i5.15958

Cited by 4 publications

(2 citation statements)

References 17 publications

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“…In the charge plasma technique, the charge carriers are motivated within the materials by employing different work functions on the drain and source regions, whereas in the electrostatic technique, the charge carriers are motivated within the materials by employing external bias [3], [4]. The tunnel field-effect transistor (TFET) device is vastly studied within the containing the virtual doping techniques [5]- [7]. TFET can be regarded as a promising alternative device of metal-oxide-semiconductors field effect transistor (MOSFET) to overcome the imperfection of short channel effects and betterment the characteristics of the device such as high ION/IOFF ratio, low OFF-current state lower subthreshold slope and minimize the power consumption [8]- [11].…”

Section: Introductionmentioning

confidence: 99%

Characterization of silicon tunnel field effect transistor based on charge plasma

Abdul-kadir

Taha

2022

IJEECS

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The aim of the proposed paper is an analytical model and realization of the characteristics for tunnel field-effect transistor (TFET) based on charge plasma (CP). One of the most applications of the TFET device which operates based on CP technique is the biosensor. CP-TFET is to be used as an effective device to detect the uncharged molecules of the bio-sample solution. Charge plasma is one of some techniques that recently invited to induce charge carriers inside the devices. In this proposed paper we use a high work function in the source (ϕ=5.93 eV) to induce hole charges and we use a lower work function in drain (ϕ=3.90 eV) to induce electron charges. Many electrical characterizations in this paper are considered to study the performance of this device like a current drain (ID) versus voltage gate (Vgs), ION/IOFF ratio, threshold voltage (VT) transconductance (gm), and sub-threshold swing (SS). The signification of this paper comes into view enhancement the performance of the device. Results show that high dielectric (K=12), oxide thickness (Tox=1 nm), channel length (Lch=42 nm), and higher work function for the gate (ϕ=4.5 eV) tend to best charge plasma silicon tunnel field-effect transistor characterization.

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Section: Introductionmentioning

confidence: 99%

Characterization of silicon tunnel field effect transistor based on charge plasma

Abdul-kadir

Taha

2022

IJEECS

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“…As Gordon Moore observed, the density of electronic components in a doubles every year, this prediction of him has become a target for miniaturization in the semiconductor industry [4]. Later Robert H. Dennard described how transistors could be scaled reliably to smaller dimensions (essence of Moore's Law) [5]. He showed how to reduce the ABSTRACT: In this paper, the MOSFET device structure has been simulated using an open-source simulator and the characterization of the ID-VG and ID-VD curves has been studied.…”

Section: Introductionmentioning

confidence: 99%

A study of MOSFET Device for The characterization of ID-VG and ID-VD Curves

Rashid,

RASHEED,

Sarhan

et al. 2022

AJEST

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In this paper, the MOSFET device structure has been simulated using an open-source simulator and the characterization of the ID-VG and ID-VD curves has been studied. The n-channel MOSFET device structure for three distinct generations has been simulated using the provided parameters, getting the corresponding I-V curves and observing their surface charge - Vg properties using the online simulator Nanohub. Based on the reported electrical characteristics, we may deduce that the Vth values decrease when the MOSFET device is scaled down. The current Id when Vg is zero is substantially higher in the third generation of the device than in the first and second generations, indicating that there is greater leakage current. Consequently, this is the punch through effect because current flows regardless of the gate voltage (i.e. even gate voltage is zero). Therefore, the device's third generation is poorly developed. In terms of performance, we can infer that the first iteration of the design is superior than the second and third generations. Therefore, substrate doping may be enhanced further for the second and third generation, while oxide thickness can be lowered further for improved performance. As the concentration of doping increases, however, we must additionally consider the influence of ionization.

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Performance Evaluation and Optimization of Graphene Nanosheet FET

Abdul-kadir,

Mohammad,

Abdulqader

et al. 2024

Preprint

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Graphene Nanosheet Field Effect Transistor (GNSFET) is constructed for the first time (using grapheme material) and simulated by Silvaco TCAD Tools it can be considered as a novelty work in Nanosheet FET design. This paper study and explore the effects of the device dimensions’ variation for 2-nanosheets GNSFET device. The variation in dimension of the gate length (Lg = 14,16 and 18) nm, gate width (Wg = 12,14 and 16) nm, and gate height (Hg = 6,7 and 8) nm are to be considered for the evaluation and optimization of the designed GNSFET performances. In addition, the performances and characteristics of the 2-nanosheets GNSFET device have been compared with that of 3- Nanosheets GNSFET device. Several nanosheet performance factors have been taken into consideration throughout the optimization process, including the following: on-current (ION), off-current (IOFF), ION/IOFF ratio, Sub threshold Swing (SS), Drain Induced Barrier Lowering (DIBL) and Trans conductance (gm). ION/IOFF ratio which represents the device switching capability is improved to 1.77e+10 at Lg=14 nm, Wg=14 nm and Hg=7 nm. The Sub Threshold Swing (SS) in this paper approaches the ideal value of 60 mV/dec which insure the device's improved gate control. The value of SS= 61.23 mV/dec at Lg = 18 nm, Wg=14 nm and Hg=7nm was obtained. The value of DIBL is between 1.28 mV/V and 31.05 mV/V. Finally, the resulted value of gm is 71.36 µS at Lg=14 nm, Wg=14 nm and Hg=7 nm.

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Investigation and design of ion-implanted MOSFET based on (18 nm) channel length

Cited by 4 publications

References 17 publications

Characterization of silicon tunnel field effect transistor based on charge plasma

Characterization of silicon tunnel field effect transistor based on charge plasma

A study of MOSFET Device for The characterization of ID-VG and ID-VD Curves

Performance Evaluation and Optimization of Graphene Nanosheet FET

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