Investigation into scaling I/O bound streaming applications productively with an all-FPGA cluster

Schmidt, Andrew G.; Datta, Siddhartha; Mendon, Ashwin A.; Sass, Ron

doi:10.1016/j.parco.2011.12.002

Cited by 8 publications

(4 citation statements)

References 29 publications

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“…This can be observed in Figure 6 and Figure 7. While detailed results can be found in [12], it was found that the speedup was most pronounced for the largest query set (12,216 bytes).…”

Section: B Applicationsmentioning

confidence: 99%

“…The AIREN network was also used to increase the productivity of I/O bound streaming applications and maintained Detailed results can be seen in [12].…”

Section: A Infrastructurementioning

confidence: 99%

“…This is basically an I/O bound streaming operation. The hardware implemented in our lab that is described in [12] accelerated Scan and Ungapped Extension functions which were based on the National Center for Biotechnology Information's (NCBI) software implementation for the same. This approach produced the same results as the NCBI implementation.…”

Section: B Applicationsmentioning

confidence: 99%

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Architecture and Applications for an All-FPGA Parallel Computer

Rajasekhar

Sass

2012

2012 41st International Conference on Parallel Processing Workshops

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The Reconfigurable Computing Cluster (RCC) project has been investigating unconventional architectures for high end computing using a cluster of FPGA devices connected by a high-speed, custom network. Most applications use the FPGAs to realize an embedded System-on-a-Chip (SoC) design augmented with application-specific accelerators to form a message-passing parallel computer. Other applications take a single accelerator core and tessellate the core across all of the devices, treating them like a large virtual FPGA. The experimental hardware has also been used for basic computer research by emulating novel architectures. This article discusses the genesis of the over-arching project, summarizes results of individual investigations that have been completed, and how this approach may prove useful in the investigation of future Exascale systems.

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“…This can be observed in Figure 6 and Figure 7. While detailed results can be found in [12], it was found that the speedup was most pronounced for the largest query set (12,216 bytes).…”

Section: B Applicationsmentioning

confidence: 99%

“…The AIREN network was also used to increase the productivity of I/O bound streaming applications and maintained Detailed results can be seen in [12].…”

Section: A Infrastructurementioning

confidence: 99%

Section: B Applicationsmentioning

confidence: 99%

See 1 more Smart Citation

Architecture and Applications for an All-FPGA Parallel Computer

Rajasekhar

Sass

2012

2012 41st International Conference on Parallel Processing Workshops

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“…The BLAST query is encoded into the 8 KByte local block. Researchers have implemented BLAST on FPGAs to demonstrate impressive speedups [19]; however, previous work [20,21] has shown that bandwidth requirements for BLAST limit the scalability such that a common bus interconnect is insufficient for transferring databases to each BLAST core as well as being used for off-chip memory lookups. Specifically, each BLAST core can sustain database input rates of 3.2 GB/s.…”

Section: Kernel Performancementioning

confidence: 99%

Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip

Kritikos

Schmidt

Sass

et al. 2012

International Journal of Reconfigurable Computing

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The reconfigurable data-stream hardware software architecture (Redsharc) is a programming model and network-on-a-chip solution designed to scale to meet the performance needs of multi-core Systems on a programmable chip (MCSoPC). Redsharc uses an abstract API that allows programmers to develop systems of simultaneously executing kernels, in software and/or hardware, that communicate over a seamless interface. Redsharc incorporates two on-chip networks that directly implement the API to support high-performance systems with numerous hardware kernels. This paper documents the API, describes the common infrastructure, and quantifies the performance of a complete implementation. Furthermore, the overhead, in terms of resource utilization, is reported along with the ability to integrate hard and soft processor cores with purely hardware kernels being demonstrated.

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